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ics for communications quad framing and line interface component for e1 / t1 / j1 quadfalc tm peb 22554 version 1.1 preliminary data sheet 09.98 ds 1
for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide: see our webpage at http://www.siemens.de/semiconductor/communication. quadfalc tm is a trademarks of siemens ag. published by siemens ag, hl sc, balanstra?e 73, 81541 mnchen ? siemens ag 1998. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. peb 22554 revision history: current version: 09.98 previous version: none page (in previous version)
peb 22554 table of contents page semiconductor group 3 09.98 1 features e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 logic symboly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2 pin descriptions e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3 functional description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.2 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3 boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.4 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.6 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.7 framer operating modes e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 3.7.1 doubleframe format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 3.7.2 crc-multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3.7.3 additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4 operational description e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.1 signaling controller operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.1.1 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 4.1.2 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 4.1.3 signaling controller functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 4.1.3.1 hdlc data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.1.3.2 hdlc data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 4.1.4 s a bit access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4.2 operational phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 4.3 specific e1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.4 control register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 4.5 status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 5 features t1 / j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 5.1 logic symboly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 5.2 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 6 pin descriptions t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 6.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 6.2 pin definitions and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 7 functional description t1 / j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 7.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 7.2 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 7.3 boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
peb 22554 semiconductor group 4 09.98 7.4 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 7.5 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 7.6 transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 7.7 framer operating modes t1 / j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 7.7.1 4-frame multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 7.7.2 12-frame multiframe (d4 or sf format) . . . . . . . . . . . . . . . . . . . . . . . . . . .250 7.7.3 extended superframe ( f24, esf format) . . . . . . . . . . . . . . . . . . . . . . . . .252 7.7.4 72-frame multiframe (slc96 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 7.7.5 additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 8 operational description t1 / j1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 8.1 signaling controller operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 8.1.1 hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 8.1.2 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 8.1.3 signaling controller functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 8.1.3.1 hdlc data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 8.1.3.2 hdlc data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 8.1.4 bit oriented message mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 8.1.5 4 kbit/s data link access in f72 format . . . . . . . . . . . . . . . . . . . . . . . . . . .276 8.2 operational phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 8.3 specific t1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 8.4 control register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 8.5 status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 9 preliminary electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .365 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 9.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 9.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 9.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 9.4.1 input/output waveforms for testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 9.4.2 master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 9.4.3 jtag boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 9.4.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 9.4.5 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 9.4.5.1 siemens/intel bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 9.4.5.2 motorola bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 9.4.6 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 9.4.7 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 9.4.8 pulse templates - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 9.4.8.1 pulse template e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 9.4.8.2 pulse template t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390 9.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 10 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .392
peb 22554 semiconductor group 5 09.98 11 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 12 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 12.1 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 12.2 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 12.3 software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
semiconductor group 6 09.98 quad framing and line interface component for e1/t1 qfalc peb 22554 cmos p-tqfp-144 type version ordering code package peb 22554-ht v1.1 q67003h9339 p-tqfp-144(smd) quadfalc in e1 mode 1 features e1 quad line interface ? high density, generic interface for all e1 / t1 / j1 applications ? quad analog receive and transmit circuitry for long/ short haul applications ? data and clock recovery using an integrated digital phase locked loop ? maximum line attenuation up to -34 db at 1024 khz adaptively controlled receive equalization network adjusts up to 4500 feet (pulp 22 awg) in length, noise - and crosstalk -filter, line attenuation status ? programmable transmit pulse shapes for e1 signals ? programmable line build-out according to ftz221 ? low transmitter output impedances for high transmit return loss ? tri-state function of the analog transmit line outputs ? transmit line monitor protecting the device from damage ? jitter specifications of itu-t i.431 , g.703 , g.736 and g.823 met ? crystal-less wander and jitter attenuation/compensation ? low frequency reference clock: 2.048mhz ? power down function per channel ? dual rail or single rail digital inputs and outputs ? unipolar nrz or cmi for interfacing fibre optical transmission routes ? selectable line codes (hdb3, ami) ? loss of signal indication with programmable thresholds according to itu-t g.775 and ets300233 ? clock generator for jitter free system/ transmit clocks per channel ? local loop and remote loop for diagnostic purposes ? ultra low power device , single power supply: 3.3 v
peb 22554 features e1 semiconductor group 7 09.98 quad frame aligner ? frame alignment/synthesis for 2.048 mbit/s according to itu-t g.704 ? programmable formats : doubleframe, crc multiframe selectable conditions for recover / loss of frame alignment ? crc4 to non-crc4 interworking of itu-t g. 706 annex b ? error checking via crc4 procedures according to itu-t g. 706 ? alarm and performance monitoring per second 16 bit counter for crc-, framing errors, code violations, error monitoring via e bit and sa6 bit, errored blocks, prbs bit errors ? insertion and extraction of alarms (ais, remote alarm ) ? idle code insertion for selectable channels ? flexible system clock frequency different for receiver and transmitter ? supports programmable system data rates: 2048 , 4096, 8192 and 16.384mbit/s with independent receive/transmit offset programming ? mux of 4 channels into a single rail 8.192 mbit/s data bus and v.v. with byte - or bitinterleaved formats ? elastic store for receive and transmit route clock wander and jitter compensation; controlled slip capability and slip indication; ? programmable elastic buffer size: 2 frames / 1 frame / short buffer / bypass ? supports fractional e1 access ? flexible transparent modes ? programmable in-band loop code detection and generation ? channel loop back , line loop back or payload loop back capabilities ? pseudo random bit sequence (prbs) generator and monitor quad signaling controller ? hdlc controller bit stuffing, crc check and generation, flag generation, flag and address recognition, handling of bit oriented functions ? cas controller with last look capability , enhanced cas- register access and freeze signaling indication ? provides access to serial signaling data streams ? multiframe synchronization and synthesis acc. to itu-t g.732 ? alarm insertion and detection (ais and los in timeslot 16) ? transparent mode ? fifo buffers (64 bytes deep) for efficient transfer of data packets. ? time-slot assignment any combination of time slots selectable for data transfer independent of signaling mode. ? time-slot 0 sa 8-4 bit handling via fifos
semiconductor group 8 09.98 peb 22554 features e1 ? hdlc access to any sa bit combination mp interface ? 8/16 bit microprocessor bus interface (intel or motorola type) ? all registers directly accessible (byte or word access) ? multiplexed and non-multiplexed address bus operations ? hard / software reset options ? extended interrupt capabilities ? one second timer (internal /external access) general ? boundary scan standard ieee 1149.1 ? p-tqfp-144 package (body size 20x20) ? 3.3 v power supply ? typical power consumption 650 mw applications ? wireless basestations ? e1/t1/j1atm gateways ? e1/t1/j1 channel & data service units (csu, dsu) ? isdn pri, pbxs ? e1/t1/j1 internet access equipement ? lan / wan router ? sonet/sdh add/ drop mux ? e1/t1/j1 multiplexer ? digital access cross-connect systems (dacs)
peb 22554 features e1 semiconductor group 9 09.98 1.1 logic symboly figure 1 quadfalc logic symbol itl10297 rclk(1-4) mclk sync sec/fsc rl1/rdip/roid(1-4) rl2/rdin/rclki(1-4) receive line interface scan boundary tms tdi tck tdo xl2/xdon/xfm(1-4) xl1/xdop/xoid(1-4) interface line transmit ddx v ssx v dd v v ss d0...15 a0...9 cs dbw ale res int microprocessor interface sclkr(1-4) rdo(1-4) rpa(1-4) rpb(1-4) rpc(1-4) receive system interface xpa(1-4) xdi(1-4) sclkx(1-4) xpc(1-4) xpb(1-4) xpd(1-4) interface system transmit im wr/rw rd/ds bhe/ble quadfalc peb 22554 tm ddr v ssr v trs rpd(1-4) (1-4) (1-4) (1-4) (1-4) (1-6) (1-6)
semiconductor group 10 09.98 peb 22554 features e1 1.2 typical applications the figures below show multiple link applications realized with the quadfalc. figure 2 4 channel e1 interface for frame relay applications its10302 peb 22554 4 x e1/t1 quadfalc tm peb 20324 m 128x cpu mem system bus pci/generic mtsl peb 2047 munich128 memory time switch
peb 22554 features e1 semiconductor group 11 09.98 figure 3 8 channel e1 interface to the atm layer its10303 quadfalc peb 22554 tm ram tm pxb 4220 iwe8 layer atm utopia pcm-highway 4 4 aal1 or atm-mode 4 x e1/t1 4 x e1/t1 peb 22554 quadfalc tm
semiconductor group 12 09.98 peb 22554 pin descriptions e1 2 pin descriptions e1 2.1 pin diagram figure 4 pin configuration of quadfalc note: all unused input pins have to be connected to a defined level ( v ss / v dd ). p-tqfp-144 peb 22554 ddx v v ssx xl1_4/xdop4/xoid4 37 144 itp10391 xl1_1/xdop1/xoid1 xl2_4/xdon4/xfm4 tdi sec/fsc tdo im rl1_1/rdip1/roid1 rl1_4/rdip4/roid4 rl2_1/rdin1/rclki1 rl2_4/rdin4/rclki4 rclk1 ale xpa1 rclk4 xpb1 xpd1 xpd3 xpc3 xpb3 trs sclkx4 mclk sync rl2_2/rdin2/rclki2 rl2_3/rdin3/rclki3 tck int tms dbw xl1_2/xdop2/xoid2 xl1_3/xdop3/xoid3 xdi1 d15 sclkx1 rpb1 rpc1 rpd1 rdo1 rdo2 sclkr2 xdi2 xdi3 sclkx3 bhe/ble cs rd/ds sclkr3 a9 a8 a7 rdo4 a5 a3 a2 a1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 38 142 39 141 40 140 139 42 138 43 137 44 136 45 135 46 134 47 133 48 132 49 131 50 130 129 52 128 53 127 54 126 55 125 56 124 57 123 58 122 59 121 60 120 119 62 118 63 117 64 116 65 115 66 114 67 113 68 112 69 111 70 110 109 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 41 71 61 51 ss v dd v v ddr v dd v ss v ddr v dd a4 a6 v ssx d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d0 d1 d2 wr/rw rl1_3/rdip3/roid3 rl1_2/rdip2/roid2 v ddr v dd v ddr ssr v ss v ssr v v ssr v ssr xl2_3/xdon3/xfm3 xl2_2/xdon2/xfm2 xl2_1/xdon1/xfm1 v ddx ddx v v ddx ssx v v ssx n.c. rclk2 rclk3 sclkr4 sclkr1 rdo3 rpa1 rpa2 rpd2 rpc2 rpb2 rpa3 rpd3 rpc3 rpb3 rpa4 rpd4 rpc4 rpb4 sclkx2 xdi4 xpc1 xpa2 xpd2 xpc2 xpb2 xpa3 xpd4 xpc4 xpb4 xpa4 v dd v ss v ss v dd v v ss dd n.c. ss v n.c. res tm quadfalc
peb 22554 pin descriptions e1 semiconductor group 13 09.98 note: all unused input pins have to be connected to a defined level ( v ss / v dd ) note: pu = if not connected an internal pull-up transistor ensure high input level. 2.2 pin definitions and functions pin no. symbol input (i) output (o) function 83 - 74 a9 a0 i address bus address bus selects one of the internal registers for read or write. 107 - 103 100 - 93 90 - 88 d15 d11 d10 d3 d2 d0 i/o data bus bi-directional three-state data lines which interface with the systems data bus. their configuration is controlled by the level of pin dbw: C 8-bit mode (dbw = 0): d0 d7 are active. d8 d15 are in high impedance and have to be connected to v dd or v ss . C 16-bit mode (dbw = 1): d0 d15 are active. in case of byte transfers, the active half of the bus is determined by a0 and bhe /ble and the selected bus interface mode (via pin im). the unused half is in high impedance. 62 ale i address latch enable a high on this line indicates an address on the external address/data bus. the address information provided on lines a0 a9 is internally latched with the falling edge of ale. this function allows the quadfalc to be directly connected to a multiplexed address/data bus. in this case, pins a0 a9 must be externally connected to the data bus pins. in case of demultiplexed mode this pin has to be connected directly to ground or v dd .
semiconductor group 14 09.98 peb 22554 pin descriptions e1 pin definitions and function (contd) pin no. symbol input (i) output (o) function 85 rd /ds i read enable (siemens/intel bus mode) this signal indicates a read operation. when the quadfalc is selected via cs the rd signal enables the bus drivers to output data from an internal register addressed via a0 a9 on to data bus. data strobe (motorola bus mode) this pin serves as input to control read/write operations. 84 wr /rw i write enable (siemens/intel bus mode) this signal indicates a write operation. when cs is active the quadfalc loads an internal register with data provided via the data bus. read/write enable (motorola bus mode) this signal distinguishes between read and write operation. 86 cs i chip select a low signal selects the quadfalc for read/ write operations. 46 res i reset a low signal on this pin forces the quadfalc into reset state. during reset the quadfalc needs an active clock on pin mclk. during reset all bi-directional output stages (data bus) arein high-impedance state if signal rd is high.
peb 22554 pin descriptions e1 semiconductor group 15 09.98 87 bhe /ble i bus high enable (siemens/intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus (d8 d15). in 8-bit bus interface mode this signal has no function and should be tied to v dd . bus low enable (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus (d0 d7). in 8-bit bus interface mode this signal has no function and should be tied to v dd . 40 dbw i data bus width (bus interface mode) a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe /ble . 41 int o/od interrupt request int serves as general interrupt request which may include all interrupt sources. these interrupt sources can be masked via registers imr0 5. interrupt status is reported via registers gis (global interrupt status) and isr0 5. output characteristics (push-pull active low/ high, open drain) are determined by programming the ipc register. 68 im i interface mode the level at this pin defines the bus interface mode: a low signal on this input selects the intel interface mode. a high signal on this input selects the motorola interface mode. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 16 09.98 peb 22554 pin descriptions e1 115, 138, 43, 66 rl1(1-4) rdip(1-4) roid(1-4) i i i line receiver 1 analog input from the external transformer. selected if lim1.drs = 0. receive data input positive digital input for received dual rail pcm(+) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive optical interface data unipolar data received from fibre optical interface with 2.048 mbit/s. latching of data is done with the falling edge of rclki. input sense is selected by bit rc0.rdis. the single rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 0. 116, 137, 44, 65 rl2(1-4) rdin(1-4) rclki(1-4) i i i line receiver 2 analog input from the external transformer. selected if lim1.drs = 0. receive data input negative input for received dual rail pcm(-) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive clock input receive clock input for the optical interface if lim1.drs = 1 and fmr0.rc1/0 = 00. clock frequency: 2048 khz pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 pin descriptions e1 semiconductor group 17 09.98 42, 67, 114, 132, 139 v ddr i positive power supply for the analog receiver. 45, 64, 117,135, 136 v ssr i power supply ground for the analog receiver 111, 142, 39, 70 xl2(1-4) xdon(1-4) xfm(1-4) o o o transmit line 2 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output negative this digital output for transmitted dual rail pcm(-) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. transmit frame marker this digital output marks the first bit of every frame. this function is only available in the optical interface mode lim1.drs=1 and fmr0.xc1 = 0. the data will be clocked off on the positive transitions of xclk. after reset this pin is in a high impedance state until register lim1.drs is set to one. in remote loop configuration the xfm marker is not valid. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 18 09.98 peb 22554 pin descriptions e1 109, 144, 37, 72 xl1(1-4) xdop(1-4) xoid(1-4) o o o transmit line 1 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output positive this digital output for transmitted dual rail pcm(+) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. transmit optical interface data unipolar data sent to fibre optical interface with 2.048 mbit/s which will be clocked off on the positive transitions of xclk. clocking off data in nrz code is done with 100 % duty cycle. data in cmi code are shifted out with 50 % or 100 % duty cycle according to the cmi coding. output sense is selected by bit lim0.xdos (after reset: data is sent active high). the single rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 0. after reset this pin is in a high impedance state until register lim1.drs is set to one. 38, 71, 110, 143 v ddx i positive power supply for analog transmitter 1, 36, 73, 108 v ssx i power supply ground for analog transmitter pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 pin descriptions e1 semiconductor group 19 09.98 133 mclk i reference clock 2.048 mhz a reference clock of 2.048 mhz +/- 50 ppm must be provided to this pin. 134 nc not connected 48 sync i + pu clock synchronization if a clock is detected at the sync pin the dco-rs of the quadfalc synchronize to this 2.048 mhz clock. this pin has an integrated pull up resistor. 69 sec fsc sec i + pu o o second timer input a pulse with logical one for at least two 2.048mhz cycles will trigger the internal second timer. enabled with gpc1.fss2-0 an 8-khz frame synchronization pulse is output via this pin. the synchronization pulse is active high / low for one 2 mhz cycle (pulse width = 488 ns). second timer output activated high every second for two 2.048 mhz clock cycles. enabled with gpc1.csfp1-0. 119, 130, 47, 61 rclk(1-4) i/o + pu receive clock after reset this port is configured to an input. setting of bit pc5.crp will switch this port to an output. input function not defined. output function: cmr1.rs1/0 = 00: receive clock extracted from the incoming data pulses. frequency: 2048 khz cmr1.rs1/0 = 01: rclk is set high in case of loss of signal (frs0.los=1). optional one of the dejittered system clocks sourced by dco-r is clocked out. clock frequency: 2048 or 8192 khz . selected by cmr1.rs1/0. wih gpc1.r1s1/0 one of the four rclk(1-4) is output on rclk1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 20 09.98 peb 22554 pin descriptions e1 8, 13, 26, 31 sclkr (1-4) i/o + pu system clock receive working clock for the receive system interface with a frequency of 16.384 / 8.192 / 4.096 / 2.048 mhz. if the receive elastic store is bypassed sic1.rbs1/0 the clock supplied on this pin is ignored. if sclkr is configured to an output, the internal working clock of the receive system interface sourced by dco-r or rclk is output. in system interface multiplex mode a 16.384 or 8.192 mhz clock has to be provided on sclkr1, which is a common clock for all 4 rec. system interfaces. 9, 12, 27, 30 rdo(1-4) o receive data out received data which is sent to the system highway. clocking off data is done with the rising or falling edge (sic3.resr) of sclkr(1-4) or rclk(1-4) if the receive elastic store is bypassed. the delay between the beginning of time-slot 0 and the initial edge of sclkr(1-4) (after sypr goes active) is determined by the values of registers rc1 and rc0. if received data is shifted out with higher data rates, the active channel phase is defined by bits sic2.sics2-0. in system interface multiplex mode all 4 received datastreams are merged into a single datastream byte or bit interleaved on rdo1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 pin descriptions e1 semiconductor group 21 09.98 4 -7, 14 -17, 22 - 25, 32 - 35 rp(a-d)1 rp(a-d)2 rp(a-d)3 rp(a-d)4 i/o + pu i + pu o o receive multifunction port a-d depending on programming of bits pc(1- 4).rpc(2-0) this multifunction ports carries information to the system interface or from the system to the quadfalc. after reset these ports are configured to inputs. with the selection of the pinfunction the in/output configuration is also achieved. depending on bit sic3.resr all outputs / inputs of the receive system interface are updated / sampled with the rising or falling edge of sclkr. synchronous pulse receive (sypr ) defines the beginning of time-slot 0 at system highway port rdo in conjunction with the values of registers rc0/1. in system interface multiplex mode sypr has to be provided at port rpa1 for all 4 channels and defines the beginning of time-slot 0 on port rdo1/rsig1. enabled with pc(1-4).rpc(2-0) = 000 (reset configuration). pulse cycle: integer multiple of 125 m s. receive frame marker (rfm) enabled with pc(1-4).rpc(2-0) = 001. cmr2.irsp = 0: the receive frame marker could be active high for a 2.048 mhz period during any bit position of the current frame. iprogramming is done with registers rc1/0. cmr2.irsp = 1: internal generated frame synchronization pulse generated by the dco-r circuitry. together with registers rc1/0 the frame begin on the receive system interface is defined. this frame synchronization pulse is active low 2.048 mhz period. receive multiframe begin (rmfb) enabled with pc(1-4).rpc(2-0) = 010. rmfb marks the beginning of every received multiframe (rdo). optionally the time-slot 16 cas multiframe begin could be marked (sic3.casmf). active high for one 2.048 mbit/s period. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 22 09.98 peb 22554 pin descriptions e1 4 -7, 14 -17, 22 - 25, 32 - 35 rp(a-d)1 rp(a-d)2 rp(a-d)3 rp(a-d)4 o o o o o receive signaling marker (rsigm) enabled with pc(1-4).rpc(2-0) = 011. marks the time-slots which are defined by register rtr1-4 of every frame on port rdo. receive signaling data (rsig) enabled with pc(1-4).rpc(2-0) = 100. the received cas signaling data is sourced by this pin. time-slots on rsig correlates directly to the time-slot assignment on rdo. in system interface multiplex mode all four received signaling datastreams are merged into a single datastream byte or bit interleaved and is transmitted on port rpb1. data link bit receive (dlr) enabled with pc(1-4).rpc(2-0) = 101. marks the sa8-4 bits within the data stream on rdo. the sa8-4 bit positions in time-slot 0 of every frame not containing the frame alignment signal are selected by register xc0. freeze signaling (freeze) enabled with pc(1-4).rpc(2-0) = 110. the freeze signaling status is active high by detecting a loss of signal alarm, or a loss of cas frame alignment or a receive slip (pos. or neg.). it will hold high for at least one complete multiframe after the alarm disappears. setting sic2.ffs enforces a high on pin freeze. frame synchronous pulse (rfsp) enabled with pc(1-4).rpc(2-0) = 111. active low framing pulse derived from the received pcm route signal. during loss of synchronization (bit frs0.lfa), this pulse is suppressed (not influenced during alarm simulation). pulse frequency: 8 khz, pulse width: 488 ns pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 pin descriptions e1 semiconductor group 23 09.98 3, 19, 21, 50 sclkx (1-4) i/o + pu system clock transmit working clock for the transmit system interface with a frequency of 16.384 / 8.192 / 4.096 / 2.048 mhz. in system interface multiplex mode a 16.384 or 8.192 mhz clock has to be provided on sclkx1, which is a common clock for all 4 transmit system interfaces. 2, 18, 20, 49 xdi(1-4) i transmit data in transmit data received from the system highway. latching of data is done with rising or falling transitions of sclkx according to bit sic3.resx. the delay between the beginning of time-slot 0 and the initial edge of sclkx (after sypx goes active) is determined by the registers xc1/0. in system interface multiplex mode latching of datastream containing the 4 frames is done byte or bit interleaved on port xdi1. in higher data rates sampling of data is defined by bits sic2.sics2-0. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 24 09.98 peb 22554 pin descriptions e1 120 - 123 126 - 129 51 - 54 57 - 60 xp(a-d)1 xp(a-d)2 xp(a-d)3 xp(a-d)4 i/o + pu i + pu i + pu transmit multifunction port a-d depending on programming of bits pc(1- 4).xpc(2-0) this multifunction ports carries information to the system interface or from the system to the quadfalc. after reset these ports are configured to inputs. with the selection of the pinfunction the in/output configuration is also achieved. depending on bit sic3.resx all outputs / inputs of the transmit system interface are updated / sampled with the rising or falling edge of sclkx synchronous pulse transmit (sypx) defines the beginning of time-slot 0 at system highway port xdi in conjunction with the values of registers xc0/1. in system interface multiplex mode sypx has to be provided at port xpa1 for all 4 channels and defines the beginning of time-slot 0 on port xdi1/xsig1. enabled with pc(1-4).xpc(2-0) = 000 (reset configuration). pulse cycle: integer multiple of 125 m s. transmit multiframe synchronization (xmfs) enabled with pc(1-4).xpc(2-0) = 001 this port defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. for correct operation of xmfs no sypx pin function should be selected for the remaining multifunction ports of the same channel. in system interface multiplex mode xmfs has to be provided at port xpb1 for all 4 channels. note: a new multiframe position has been settled at least one multiframe after pulse xmfs has been supplied. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 pin descriptions e1 semiconductor group 25 09.98 120 - 123 126 - 129 51 - 54 57 - 60 xp(a-d)1 xp(a-d)2 xp(a-d)3 xp(a-d)4 i + pu i + pu o o o o transmit signaling data (xsig) enabled with pc(1-4).xpc(2-0) = 010. input for transmit signaling data received from the signaling highway. optionally (sic3.ttrf) sampling of xsig data is controlled by the active high xsigm marker. in higher data rates sampling of data is defined by bits sic2.sics2- 0. in system interface multiplex mode latching of the datastream containing the 4 signaling multiframes is done byte or bit interleaved on port xpc1. transmit clock (tclk) enabled with pc(1-4).xpc(2-0) = 011. a 2.048 / 8.192 mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) should not be used. optional this input functions as a synchronization clock for the dco-x circuitry with a frequency of 2.048 mhz clock. transmit multiframe begin (xmfb) xmfb marks the beginning of every transmitted multiframe (xdi). active high for one 2.048 mbit/s period. enabled with pc(1- 4).xpc(2-0) = 100. transmit signaling marke r (xsigm) marks the transmit time-slots which are defined by register ttr1-4 of every frame transmitted via port xdi. enabled with pc(1-4).xpc(2-0) = 101. data link bit transmit (dlx) marks the sa8-4 bits within the data stream on xdi. the sa8-4 bit positions in time-slot 0 of every frame not containing the frame alignment signal are selected by register xc0.sa8e- sa4e. enabled with pc(1-4).xpc(2-0) = 110. transmit clock (xclk) transmit line clock, frequency: 2.048 mhz derived from sclkx/r, rclk or internally generated by the dco-x circuitry. enabled with pc(1-4).xpc(2-0) = 111. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 26 09.98 peb 22554 pin descriptions e1 11, 29, 56, 92, 102, 125, v ss i power ground supply for digital subcircuits (0 v) for correct operation, all six pins have to be connected to ground. 10, 28, 55, 91, 101, 124, v dd i positive power supply for the digital subcircuits (3.3 v) for correct operation, all six pins have to be connected to positive power supply. 112 tdi i + pu test data input for boundary scan acc. to ieee std. 1149.1 113 tdo o test data output for boundary scan 141 tms i + pu test mode select for boundary scan 140 tck i + pu test clock for boundary scan 131 trs i + pu test reset for boundary scan (active low) if the jtag boundary scan is not used this pin can be connected to pin res or vss. 63, 118 rsvd i/o + pu reserved pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 pin descriptions e1 semiconductor group 27 09.98
peb 22554 functional description e1 semiconductor group 28 09.98 3 functional description e1 3.1 functional block diagram figure 5functional block diagram peb 22554 its10300 long+short haul line interface clock/data recovery haul transmit long + short local loop line decoder alarm detector receive framer frame gen. alarm gen. line coding perform. monitor. or buffer receive elastic cas-br signaling controller cas-cc remote loop + jatt bypass bypass transmit elastic buffer or payload loop transmit backplane interface interface backplane receive controller hdlc/bom rdo(1-4) rpa(1-4) rpb(1-4) rpc(1-4) xpc(1-4) xpb(1-4) xpa(1-4) xdi(1-4) sclkx(1-4) sclkr(1-4) sec/fsc sync mclk d0...15 a0...9 falc 1 rclk(1-4) xoid(1-4) xl2/xdon/ roid(1-4) intel/motorola microprocessor interface clocking unit boundary scan jtag 1149 sclkx (1-4) receive jitter attenuator rl2/rdin/ attenuator transmit jitter rclk tdi tms tck trs tdo cs wr/rw rd/ds ale bhe/ble im dbw int tclk xpd(1-4) rl1/rdip/ rclki(1-4) xl1/xdop/ xfm(1-4) (1-4) rclk tclk (1-4) rpd(1-4) prbs monitor prbs generator line interface falc 2 falc 3 falc 4 res
peb 22554 functional description e1 semiconductor group 29 09.98 3.2 microprocessor interface the communication between the cpu and the quadfalc is done via a set of directly accessible registers. the interface may be configured as siemens/intel or motorola type with a selectable data bus width of 8 or 16 bits. the cpu transfers data to/from the quadfalc (via 64 byte deep fifos per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe /ble as shown in table 1 and 2 . in table 3 is shown how the ale (address latch enable) line is used to control the bus structure and interface type. the switching of ale allows the quadfalc to be directly connected to a multiplexed address/data bus. mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and xfifo of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access to the fifos is allowed without any restrictions. table 1 data bus access (16-bit intel mode) bhe a0 register access quadfalc data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d8 C d15 1 0 register byte access (even addresses) d0 C d7 1 1 no transfer performed none
peb 22554 functional description e1 semiconductor group 30 09.98 table 2 data bus access (16-bit motorola mode) table 3 selectable bus and microprocessor interface configuration the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: siemens/intel (adr. n + 1) (adr. n) motorola (adr. n) (adr. n + 1) -- n: even address complete information concerning register functions is provided in C detailed register description. fifo structure in transmit and receive direction of the signaling controller 64-byte deep fifos for each channel are provided for the intermediate storage of data between the system internal highway and the cpu interface. the fifos are divided into two halves of 32-bytes. only one half is accessible to the cpu at any time. ble a0 register access quadfalc data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d0 C d7 1 0 register byte access (even addresses) d8 C d15 1 1 no transfer performed none ale im microprocessor interface bus structure gnd/vdd 1 motorola demultiplexed gnd/vdd 0 intel demultiplexed switching 0 intel multiplexed data lines d15 d8 d7 d0
peb 22554 functional description e1 semiconductor group 31 09.98 in case 16-bit data bus width is selected by fixing pin dbw to logical 1 word access to the fifos is enabled. data output to bus lines d0-d15 as a function of the selected interface mode is shown in figure 6 and 7 . of course, byte access is also allowed.the effective length of the accessible part of rfifo can be changed from 32 bytes (reset value) down to 2 bytes independent for each channel. figure 6 fifo word access (intel mode) 32 1 32 rfifo byte 4 byte 3 byte 2 byte 1 1 2 3 4 d15 d8 d7 d0 d0 d7 d8 d15 4 3 2 1 byte 1 byte 2 byte 3 byte 4 xfifo 32 1 32 itd01798
peb 22554 functional description e1 semiconductor group 32 09.98 figure 7 fifo word access (motorola mode) 32 1 32 rfifo byte 4 byte 3 byte 2 byte 1 1 2 3 4 d15 d8 d7 d0 d0 d7 d8 d15 4 3 2 1 byte 1 byte 2 byte 3 byte 4 xfifo 32 1 32 itd01799
peb 22554 functional description e1 semiconductor group 33 09.98 interrupt interface special events in the quadfalc are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; ipc register), which requests the cpu to read status information from the quadfalc, or to transfer data from/to quadfalc. since only one int request output is provided, the cause of an interrupt must be determined by the cpu by reading the quadfalc s interrupt status registers (cis, gis, isr0-4) that means the interrupt on pin int and the interrupt status bits are reset by reading the interrupt status registers. register isr0-4 are from type clear on read. the structure of the interrupt status registers is shown in figure 8 . figure 8 quadfalc interrupt status register structure each interrupt indication of registers isr0-4 can be selectively masked by setting the corresponding bit in the corresponding mask registers imr0-4. if the interrupt status bits are masked, they neither generate an interrupt at int nor are they visible in isr0-4. cis, the non-maskable channel interrupt status register, serves as a pointer to pending channel related global interrupt status registers. after the quadfalc has requested an interrupt by activating its int pin, the cpu should first read the channel interrupt status its10309 isr0 isr1 isr3 isr2 isr3 imr3 imr0 isr0 isr1 imr1 imr2 isr2 isr4 imr4 isr4 c1 c2 c4 c3 channel interrupt status global interrupt status (per channel) gis cis
peb 22554 functional description e1 semiconductor group 34 09.98 register cis to identify the requesting channel. the global interrupt status register serves itself as a pointer to pending interrupt status registers isr0 -4 for each channel. after reading the assigned global interrupt status register and the assigned interrupt status registers isr0- 4, the pointer in the gis and cis registers are cleared or updated if another interrupt requires service. if all pending interrupts are acknowledged by reading (cis and gis are reset), pin int goes inactive. updating of interrupt status registers isr04 , gis and cis is only prohibited during read access. masked interrupts visible in status registers the channel and global interrupt status registers indicates those interrupt status registers with active interrupt indications. an additional mode may be selected via bit ipc.vis. in this mode, masked interrupt status bits neither generate an interrupt on pin int nor are they visible in cis and gis, but are displayed in the respective interrupt status register(s) isr0..4 . this mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. notes: ? in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. ? all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no hierarchical polling possible), since gis only contains information on actually generated - i.e. unmasked-interrupts. 3.3 boundary scan interface identification register: 32 bit version: 1 h part number: 004d h manufacturer: 083 h in quadfalc a test access port (tap) controller is implemented. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes
peb 22554 functional description e1 semiconductor group 35 09.98 of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard: ieee 1149.1. figure 9 gives an overview. figure 9 block diagram of test access port and boundary scan test handling is performed via the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output). test data at tdi are loaded with a 4-mhz clock signal connected to tck. 1 or 0 on tms causes a transition from one controller state to an other; constant 1 on tms leads to normal operation of the chip. if no boundary scan testing is planned tms and tdi do not need to be connected since pull-up transistors ensure high input levels in this case. nevertheless it would be a good practice to put the unused inputs to defined levels. in this case, if the jtag is not used: tms = tck = 1. after switching on the device ( v dd = 0 to 3.3 v) pin trs has to reset which forces the tap controller into test logic reset state. clock generation clock reset reset tap controller -finite state machine -instruction register (3 bits) -test signal generator tck tms tdi tdo clock test control data in control bus 6 id data out ss data out bs data in identification scan (32 bits) boundary scan (n bits) 1 2 n pins itb10938 enable data out test access port trs tap controller reset
peb 22554 functional description e1 semiconductor group 36 09.98 3.4 receive path figure 10 receive clock system receive line interface for data input, three different data types are supported: ? ternary coded signals received at multifunction ports rl1 and rl2 from a -34 db ternary interface. the ternary interface is selected if lim1.drs is reset. ? digital dual rail signals received at ports rdip and rdin. the dual rail interface is selected if lim1.drs and fmr0.rc1 is set. ? unipolar data at port roid received from a fibre optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1 is reset. long haul interface the quadfalc has an integrated short- and long- haul line interface, comprising a receive equalization network and noise filtering. its10306 clock & data recovery line decoder rdata rdp rdn rclk analog- los detector alarm detector peak detector sync rclk rl1/ rl2/ rdip/ roid rdin/ rclki equalizer dco-r receive jitter attenuator receive fsc system interface clocking unit mclk rclk
peb 22554 functional description e1 semiconductor group 37 09.98 receive equalization network the quadfalc automatically recovers the signals received on pins rl1/2 in a range of up to -34 db. the maximum reachable length with a 22 awg twisted-pair cable is 1500 m . after reset the quadfalc is in ?short haul mode, received signals are recovered up to -10 db of cable attenuation. switching in ?long haul mode is done by setting of register lim0.eqon. the integrated receive equalization network recovers signals with up to -34 db of cable attenuation. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak detected and sliced at 55% of the peak value to produce the digital data stream. the received data is then forwarded to the clock & data recovery unit. receive line attenuation indication status register res reports the current receive line attenuation in a range from 0 to -34 db in 25 steps of approximately 1.4 db each. the least significant 5 bits of this register indicate the cable attenuation in db. these 5 bits are only valid in conjunction with the most significant two bits (res.ev1/0 = 01) . receive clock and data recovery the analog received signal at port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal at port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rclk from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single rail, unipolar bit stream. the clock and data recovery works with the internally generated high frequency clock based on mclk. normally the clock that is output via pin rclk is the recovered clock from the signal provided by rl1/2 or rdip/n has a duty cycle close to 50 %. the free run frequency is defined by mclk = 2.048 mhz in periods with no signal. the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ui. in digital bipolar line interface mode the clock and data recovery will accept only hdb3 coded signals with 50 % duty cycle. receive line coding the hdb3 line code or the ami coding is provided for the data received from the ternary or the dual rail interface. in case of the optical interface a selection between the nrz code and the cmi code (1t2b) with hdb3 postprocessing is provided. if cmi code (1t2b) is selected the receive route clock will be recovered from the data stream. the 1t2b decoder does not correct any errors. in case of nrz coding data will be latched with the falling edge of pin rclki. the hdb3 code is used along with double violation detection or extended code violation detection (selectable). in ami code all code violations will be detected. the detected errors increment the code violation counter (16 bits length).
peb 22554 functional description e1 semiconductor group 38 09.98 when using the optical interface with nrz coding, the decoder is by-passed and no code violations will be detected. the signal at the ternary interface is received at both ends of a transformer. the operating modes 75 or 120 w are selectable by switching resistors in parallel. this selection does not require changing transformers. figure 11 receiver configuration recommended receiver configuration values loss of signal detection there are different definitions for detecting loss of signal (los) alarms in the itu-t g.775 and ets 300233. the quadfalc covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable via register ipc.sci. ? detection: an alarm will be generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. no pulse in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for no pulse in the analog receive interface (lim1.drs=0). the receive signal level q is programmable via three control bits lim1.ril2-0 in a range of about 900 to 50 mv differential voltage between pins rl1/2. the number n can be set via an 8 bit register pcd. the contents of the pcd register will be multiplied by 16, which results in the number of pulse periods or better, the time which has to suspend until the alarm has to be detected. the range results parameter characteristic impedance [ w ] 120 75 r 1 ( 1 %) [ w ] 100-120 75 t 2 : t 1 1 : 1 1 : 1 its10967 line t 2 t 1 rl2 rl1 2 r r falc
peb 22554 functional description e1 semiconductor group 39 09.98 therefore from 16 to 4096 pulse periods. ets300233 requires detection intervals of at least 1 ms. this time period results always in a lfa (loss of frame alignment) before a los will be detected. ? recovery: in general the recovery procedure starts after detecting a logical one (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril2-0) of the nominal pulse. the value in the 8 bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions may be programmed by register lim2. receive jitter attenuator the receive jitter attenuator is placed for each channel in the receive path. the working clock is an internally generated high frequency clock based on the clock provided on pin mclk (2.048 mhz). the jitter attenuator meets the requirements of itu-t i.431, g. 736-739, g.823 and etsi tbr12/13. the internal pll circuitry dco-r generates an ?jitterfree output clock which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock.the receive jitter attenuator could be either synchronized to the extracted receive clock rclk or to a 2.048 mhz clock provided on pin sync. the received data is written into the receive elastic buffer with rclk and are read out with the dejittered clock sourced by dco-r. the jitter attenuated clock could be output via pins rclk or sclkr. optionally a 8 khz clock is provided on pin sec/fsc. the dco-r circuitry attenuates the incoming jittered clock starting at 2 hz jitter frequency with 20 db per decade fall off. wander with a jitter frequency below 2 hz will be passed unattenuated. the intrinsic jitter in the absence of any input jitter is < 0.02 ui. for some applications it might be useful starting of jitter attenuation at lower frequencies. therefore the corner frequency is switchable by the factor of ten downto 0.2 hz (lim2.scf). the dco-r circuitry is automatically centered to the nominal bit rate if the reference clock on pin sync / rclk is missed for two 2.048 mhz clock periods. this center function of dco-r may be optionally disabled (cmr2.dcf = 1) in order to accept a gapped reference clock. in analog line interface mode the rclk is always running. only in digital line interface mode with single rail data a gapped clock may occur.
peb 22554 functional description e1 semiconductor group 40 09.98 the receive jitter attenuator works in two different modes: ? slave mode in slave mode (lim0.mas = 0) the dco-r will be synchronized to the recovered route clock. in case of los the dco-r switches automatically to master mode. if bit cmr1.dcs is set automatic switching from rclk to sync is disabled. ? master mode in master mode (lim0.mas = 1) the jitter attenuator is in free running mode if no clock on pin sync is supplied. if a c2.048 mhz clock at the sync input is applied the dco-r will synchronize to this input. the following table shows the clock modes with the corresponding synchronization sources. mode internal los active sync input system clocks generated by dco-r master independent fixed to vdd dco-r centered, if cmr2.dcf =0. (cmr2.dcf should not be set) master independent 2 mhz synchronized on sync input (external 2 mhz) slave no fixed to vdd synchronized on line rclk1-4 , selected by cmr1.drss1/0 slave no 2 mhz synchronized on line rclk1-4 , selected by cmr1.drss1/0 slave yes fixed to vdd cmr1.dcs = 0: dco-r is centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) cmr1.dcs = 1: synchronized on line rclk1-4, selected by cmr1.drss1/0 slave yes 2 mhz cmr1.dcs = 0: synchronized on sync input (external 2.048 mhz) cmr1.dcs = 1: synchronized on line rclk1-4, selected by cmr1.drss1/0
peb 22554 functional description e1 semiconductor group 41 09.98 the jitter attenuator meets the jitter transfer requirements of the rec. i.431 and g.735-739 (refer to figure 12 ). figure 12 jitter attenuation performance also the requirements of etsi tbr12/13 will be satisfied. insuring adequate margin against tbr12/13 output jitter limit with 15 ui input at 20 hz the dco-r circuitry will start jitter attenuation at nearly 2 hz. itd10312 1 -60 frequency attenuation 10 100 1000 10000 100000 hz itu g.736 template -50 -40 -30 -20 -10 0 10 db falc r
peb 22554 functional description e1 semiconductor group 42 09.98 jitter tolerance the quadfalc receivers tolerance to input jitter complies to itu for cept application. figure 13 shows the curves of different input jitter specifications stated below as well as the quadfalc performance. figure 13 jitter tolerance output jitter in the absence of any input jitter the quadfalc generates the output jitter, which is specified in the table below.. transmit jitter attenuator the transmit jitter attenuator dco-x circuitry generates a ?jitterfree transmit clock for each channel and meets the following requirements: itu-t i.431, g. 703, g. 736-739, g.823 and etsi tbr12/13. the dco-x circuitry works internally with the same high frequency clock as the receive jitter attenuator it does. it synchronizes either to the working clock of the transmit backplane interface or the clock provided by pin tclk or specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff itu-t i.431 20 hz 100 khz < 0.015 700 hz 100 khz < 0.015 itd10308 1 0.1 jitter frequency jitter amplitude 10 100 1000 10000 100000 ui hz pub 62411 1 10 100 1000 tr-nwt 000499 cat ii ccitt g.823 itu-t i.431 falc r
peb 22554 functional description e1 semiconductor group 43 09.98 the receive clock rclk (remote loop / loop-timed). the dco-x attenuates the incoming clock jitter starting at 2 hz with 20 db per decade fall off. with the jitter attenuated clock, which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the jatt buffer (2 frames, remote loop) wander with a jitter frequency below 2 hz are passed transparently. the dco-x accepts gapped clocks which are used in atm or sdh/sonet applications. the jitter attenuated clock is output by pin xclk. the transmit jitter attenuator could be disabled. in that case data is read from the transmit elastic buffer with the clock sourced by pin tclk (2.048 or 8.192 mhz). synchronization between sclkx and tclk has to done externally. in the loop-timed clock configuration (lim2.elt) the dco-x circuitry generates a transmit clock which is frequency synchronized to rclk. in this configuration the transmit elastic buffer has to be enabled. figure 14 transmit clock system note: dr = dual rail interface dco-x digital controlled oscillator transmit its10305 pulse shaper d jitter framer sclkx xl1/ xdop/ xl2/ xdon xclk a xoid dr dr elastic store xdi rclk tclk transmit attenuator dco-x sclkr internal clock of receive system tclk 4 clocking unit mclk (e1: 8mhz) interface transmit (t1: 6mhz) e1: 8mhz t1: 6mhz
peb 22554 functional description e1 semiconductor group 44 09.98 framer/synchronizer the following functions are performed: ? synchronization on pulse frame and multiframe ? error indication when synchronization is lost. in this case, ais is automatically sent to the system side and remote alarm to the remote end if en/disabled. ? initiating and controlling of resynchronization after reaching the asynchronous state. this may be automatically done by the quadfalc, or user controlled via the microprocessor interface. ? detection of remote alarm indication from the incoming data stream. ? separation of service bits and data link bits. this information is stored in status registers. ? generation of various maskable interrupt statuses of the receiver functions. ? generation of control signals to synchronize the crc checker, and the receive elastic buffer. if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc submultiframe according to the crc 4 procedure ( refer to itu-t rec. g704 ). these bits are compared with those check bits that are received during the next crc submultiframe. if there is at least one mismatch, the crc error counter (16 bit) will be incremented. receive elastic buffer the received bit stream is stored in the receive elastic buffer. the memory is organized as a two-frame elastic buffer with a maximum size of 64 8 bit. the size of the elastic buffer can be independently configured for the receive and transmit direction. programming of the receive buffer size is done by sic1.rbs1/0 : ? rbs1/0 = 00 : two frame buffer or 512 bits maximum of wander amplitude (peak-to-peak): 190 ui (1 ui = 488 ns ) average delay after performing a slip: 1 frame or 256 bits ? rbs1/0 = 01 : one frame buffer or 256 bits max. wander amplitude: 100 ui average delay after performing a slip: 128 bits, (sypr = output) ? rbs1/0 = 10 : short buffer or 96 bits : max. wander amplitude: 38 ui average delay after performing a slip: 48 bits, (sypr = output) ? rbs1/0 = 11 : bypass of the receive elastic buffer the functions are: ? clock adaption between system clock (sclkr) and internally generated route clock (rclk). ? compensation of input wander and jitter. ? frame alignment between system frame and receive route frame
peb 22554 functional description e1 semiconductor group 45 09.98 ? reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data which is circularly written to the elastic buffer using internally generated receive route clock (rclk). reading of stored data is controlled by the system clock sourced by sclkr or by the receive jitter attenuator and the synchronous pulse (sypr ) in conjunction with the programmed offset values for the receive time-slot/clock-slot counters. after conversion into a serial data stream, the data is given out via port rdo. if the receive buffer is bypassed programming of the time-slot offset is disabled and data is clocked off with rclk instead of sclkr. in one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or 46 bits. in bypass mode the time-slot assigner is disabled. in this case sypr programmed as input is ignored. slips will be performed in all buffer modes except the bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. the following table gives an overview of the receive buffer operating mode . in single frame mode ( sic1. rbs) , values of receive time-slot offset (rc1/0) have to be specified great enough to prevent too great approach of frame begin (line side) and frame begin (system side). figure 15 gives an idea of operation of the receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s +, s C). if a slip condition is detected, a negative slip (one frame or one half of the current buffer size is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rclk and the current working clock of the receive backplane interface. i.e. on the position of 1) in bypass mode the clock provided on pin sclkr is ignored. clocking is done with rclk. buffer size (sic1.rbs1/0) ts offset program. (rc1/0) + sypr = input slip perform. bypass 1) disabled recom. sypr = output no short buffer not recommended, recom. sypr = output yes 1 frame not recommended, recom. sypr = output yes 2 frames enabled yes
peb 22554 functional description e1 semiconductor group 46 09.98 pointer r and w within the memory. a positive / negative slip is indicated in the interrupt status bits isr3.rsp and isr3.rsn. figure 15 the receive elastic buffer as circularly organized memory limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r' s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip
peb 22554 functional description e1 semiconductor group 47 09.98 receive signaling controller each of the four signaling controller can be programmed to operate in various signaling modes. the quadfalc will perform the following signaling and data link methods: ? hdlc or lapd access in case of common channel signaling the signaling procedure hdlc/sdlc or lapd according to q.921 will be supported. the signaling controller of the quadfalc performs the flag detection , crc checking, address comparisson and zero bit-removing. the received data flow and the address recognition features can be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the quadfalc performs a 1 or 2 byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) and will be excluded from the address comparison. buffering of receive data is done in a 64 byte deep rfifo. refer also to chapter 4.1 . in signaling controller transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit-stuffing. this allows user specific protocol variations. the quadfalc offers the flexibility to extract data during certain time-slots. any combination of time-slots may be programmed independently for the receive and transmit direction. ? s a bit access the quadfalc supports the s a bit signaling of time-slot 0 of every other frame as follows: - the access via registers rsw - the access via registers rsa4-8, capable of storing the information for a complete multiframe - the access via the 64 byte deep receive fifo of the signaling controller. this s a bit access gives the opportunity to receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. any combination of s a bits which should be extracted and stored in the rfifo may be selected by xc0.sa8-4. the access to the rfifo is supported by isr0.rme / rpf. ? channel associated signaling cas the signaling information is carried in time-slot 16 (ts16). receive data is stored in registers rs1-16 on the cas multiframe boundary. the signaling controller samples the bit stream either on the receive line side or if external signaling is enabled on the receive system side. external signaling is enabled by selecting the rsig pinfunction via register pc1-4. optionally the complete cas multiframe may be transmitted on pin rsig. the signaling data is clocked out with the working clock of the receive highway (sclkr) in conjunction with the rec. synchron. pulse (sypr ). data on rsig will be transmitted
peb 22554 functional description e1 semiconductor group 48 09.98 in the last 4 bits per time-slot and are aligned to the data on rdo. the first 4 bits per time-slot could be optionally fixed high or low, except time-slot 0 and 16. in time-slot 0 the fas / nfas word is transmitted, in time-slot 16 the cas multiframe pattern. data on rsig are only valid if the freeze signaling status is inactive. with fmr1.sais an all ones may be transmitted on rdo and rsig. the signaling procedure will be done as it is described in itu-t g.704 and g.732. the main functions are: - synchronization to a cas multiframe - detection of ais and remote alarm in cas multiframes - separation of cas service bits x1-x3 - storing of received signaling data in registers rs1-16 with last look capability updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss of signal, or a loss of cas multiframe alignment or a receive slip occurs. the current freeze status is output on port freez (rpa-d) and indicated by register sis.sfs. if sis.sfs is active updating of the registers 1-16 is disabled. optionally automatic freeze signaling may be disabled by setting bit sic3.daf. to relieve the p load from always reading the complete rs1-16 buffer every 2 msec the quadfalc notifies the p via interrupt isr0.casc only when signaling changes from one multiframe to the next. additionally the quadfalc generates a receive signaling data change pointer (rsp1/2) which directly points to the updated rs1-16 register .
peb 22554 functional description e1 semiconductor group 49 09.98 3.5 system interface the quadfalc offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. the interface to the receive system highway is realized by two data buses, one for the data rdo and one for the signaling data rsig. the receive highway is clocked via pin sclkr, while the interface to the transmit system highway is independently clocked via pin sclkx. the frequency of these working clocks and the data rate of 2.048 / 4.096 / 8.192 / 16.384 mbit/s for the receive and transmit system interface is programmable by sic1.ssc1/0 , and sic1.ssd1, fmr1.ssd0. selectable system clock and data rates and their valid combinations are shown in the table below table 4 system clocking and data rates x = valid , -- = invalid generally the data or marker on the system interface are clocked off or latched on the rising or falling edge (sic3.resr/x) of the sclkr/x clock. some clocking rates allow transmitting of time-slots in different channel- phases. each channel-phase which should be active on ports rdo, xdi, rp(a-d) and xp(a-d) is programmable by sic2.sics2-0, the remaining channel-phases are cleared or ignored. the signals on pin sypr in conjunction with the assigned timeslot offset in register rc0 and rc1 will define the beginning of a frame on the receive system highway.the signal on pin sypx in conjunction with the assigned timeslot offset in register xc0 and xc1 will define the beginning of a frame on the transmit system highway. adjusting the frame begin (time-slot 0, bit 0) relative to sypr/x is possible in the range of 0 - 125 sec. the minimum shift of varying the time-slot 0 begin could be programmed between 1 bit and 1/8 bit depending of the system clocking and data rate. e.g. with a clocking / data rate of 2.048 mhz shifting is done bitwise, while running the quadfalc with 16.384 mhz and 2.048 mbit/s data rate it is done by 1/8 bit. a receive frame marker rfm could be activated during any bit position of the entire frame. programming is done with registers rc1/0. the pin function rfm is selected by pc(1-4).rpc(2-0) = 001. the rfm selection disables the internal time-slot assigner, no offset programming is performed. the receive frame marker is active high for one system data rate clock rate 2.048 mhz clock rate 4.096 mhz clock rate 8.192 mhz clock rate 16.384 mhz 2.048 mbit/s xxxx 4.096 mbit/s --xxx 8.192 mbit/s -- -- x x 16.384 mbit/s -- -- -- x
peb 22554 functional description e1 semiconductor group 50 09.98 2.048 mhz cycle and is clocked off with the rising or falling edge of the clock which is in/output on port sclkr. figure 16 system interface system interface multiplex mode setting this bit enables a single rail data stream of 16.384 or 8.192 mbit/s containg all four e1 frames. the receive system interface for all four channels is running with the clock provided on sclkr1 and the frame sync pulse provided on sypr1 . the transmit system interface is running with sclkx1 and sypx1 . data will be transmitted / accepted its10298 buffer receive elastic buffer backplane receive rsigm rsig rmfb rfm dlr freez rfspq rp(a-d) syrpq dco-r rdo sclkx backplane transmit xclk xsigm xmfb dlx tclk xmfs sypxq xsig xp(a-d) signaling transmit elastic buffer transmit xdi signaling buffer receive jitter attenuator dco-r receive clock transmit jitter attenuator tclk rclk byp. plb transmit data transmit clock receive data byp. dco-r sclkr receive
peb 22554 functional description e1 semiconductor group 51 09.98 in a byte or bit interleaved format. bit interleaving is valid with the 16.384 or 8.192 mhz clocking rates. all four single channel falcs(1-4) have to be configured equally with the following parameters: ? clocking rate : 16.384 / 8.192 mhz , sic1.ssc1/0 ? data rate : 16.384 / 8.192 mbit/s, sic1.ssd1, fmr1.ssd0 ? time-slot offset programming : rc1/0 , xc1/0 ? receive buffer size : sic1.rbs1/0 = 00 (2 frames) the multiplexed data stream is internal logically ored. therefore the selection of the active channel phase have to be configured different for each single channel falc. programming is done with sic2.sics2-0. in system interface multiplex mode signals on rdo2-4 and rsig2-4 are undefined, while signals on sclkr2-4, sypr 2-4, sclkx2-4, sypx 2-4, xdi2-4 and xsig2-4 are ignored.
peb 22554 functional description e1 semiconductor group 52 09.98 figure 17 receive system interface clocking itd10951 ~ ~ ~ ~ frame 1 frame 2 frame 3 frame 15 frame 16 frame 1 frame 2 frame 15 ~ ~ ~ ~~ ~ ~ ~ ~ ~ bit 255 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 2 bit 1 bit 0 bit 255 t multi frame 1 multi frame 2 4 mbit interface 2 mbit interface programmable via rc0/1 rdo rmfb sypr sypr sclkr 8.192 mhz 2.048 mhz sclkr 2 mbit/s data rate rdo/rsig ts0 rdo/rsig (sclkr = 8.192 mhz) 4 mbit/s data rate dlr sa-bit marker xc0 . sa8e-sa4e receive frame marker rfm rc0/1 rsigm time-slot marker rtr1...4 4 mbit/s data rate (sclkr = 8.192 mhz) rdo/rsig trigger edge edge sample marks any sa bit bit position marks any marks any time-slot 4 mbit interface 2 mbit interface bit 3 bit 4 bit 5 bit 6 bit 7 1) only falling trigger edge shown, depending on bit sic3.resr 1)
peb 22554 functional description e1 semiconductor group 53 09.98 figure 18 2.048 mhz receive signaling highway time-slot assigner the quadfalc offers the flexibility to connect data during certain time-slots, as defined by registers rtr1-4 and ttr1-4, to the rfifo and xfifo, respectively. any combinations of time-slots can be programmed for the receive and transmit directions. if ccr1.eits = 1 the selected time-slots (rtr1-4) will be stored in the rfifo of the signaling controller and the xfifo contents will be inserted into the transmit path as controlled by registers ttr1-4. itt10517 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a fas / nfas ts0 ts1 ts31 ts31 125 m s t sypr sclkr rdo rsig t = time-slot offset (register rc1/0) = frame alignment signal fas = ts0 not containing the fas word nfas = signaling bits for time-slot 1-30 of cas multiframe abcd ~ ~
peb 22554 functional description e1 semiconductor group 54 09.98 table 5 time-slot assigner time-slots receive time-slot register transmit time-slot register rtr1.7 rtr1.6 rtr1.5 rtr1.4 rtr1.3 rtr1.2 rtr1.1 rtr1.0 rtr2.7 rtr2.6 rtr2.5 rtr2.4 rtr2.3 rtr2.2 rtr2.1 rtr2.0 rtr3.7 rtr3.6 rtr3.5 rtr3.4 rtr3.3 rtr3.2 rtr3.1 rtr3.0 rtr4.7 rtr4.6 rtr4.5 rtr4.4 rtr4.3 rtr4.2 rtr4.1 rtr4.0 ttr1.7 ttr1.6 ttr1.5 ttr1.4 ttr1.3 ttr1.2 ttr1.1 ttr1.0 ttr2.7 ttr2.6 ttr2.5 ttr2.4 ttr2.3 ttr2.2 ttr2.1 ttr2.0 ttr3.7 ttr3.6 ttr3.5 ttr3.4 ttr3.3 ttr3.2 ttr3.1 ttr3.0 ttr4.7 ttr4.6 ttr4.5 ttr4.4 ttr4.3 ttr4.2 ttr4.1 ttr4.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
peb 22554 functional description e1 semiconductor group 55 09.98 3.6 transmit path compared to the receive paths the inverse functions are performed for the transmit direction. the interface to the transmit system highway is realized by two data buses, one for the data xdi and one for the signaling data xsig. the time-slot assignment is equivalent to the receive direction. latching of data is controlled by the system clock (sclkx) and the synchronous pulse (sypx / xmfs) in conjunction with the programmed offset values for the transmit time-slot/clock-slot counters xc1/0. the frequency of the working clock of 2.048 / 4.096 / 8.192 / 16.384 mhz for the transmit system interface is programmable by sic1.ssc1/0. refer also table 4 . the received bit stream on ports xdi and xsig could be multiplexed internally on a time-slot basis, if enabled by sic3.ttrf = 1. the data received at port xsig could be sampled if the transmit signaling marker xsigm is active high. data at port xdi will be sampled if xsigm is low for the respective time-slot. programming the xsigm marker is done with registers ttr1-4. figure 19 2.048 mhz transmit signaling highway itt10518 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a fas / nfas ts0 ts1 ts31 ts31 125 m s t sypx sclkx xdi xsig t = time-slot offset (register xc1/0) = frame alignment signal fas = ts0 not containing the fas word nfas = signaling bits for time-slot 1-30 of cas multiframe abcd ~ ~
peb 22554 functional description e1 semiconductor group 56 09.98 figure 20 transmit system interface clocking: 2.048 mhz frame0 frame1 frame2 frame15 frame0 frame1 frame2 multi frame 1 multi frame 2 xdi xmfb xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi/xsig bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 dlx sa-bit marker xc0.sa8e-sa4e bit 4 marked transmit clocking e1 rev.1.0 1) only falling edge mode shown 2) delay t is programmable by xc0/1; sypx t 2) xsigm ts0
peb 22554 functional description e1 semiconductor group 57 09.98 figure 21 transmit system interface clocking: 8.192 mhz and 4.096 mbit/s frame0 frame1 frame2 frame15 frame0 frame1 frame2 multi frame 1 multi frame 2 xdi xmfb xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi/xsig sic2.sics2-0=000 dlx sa-bit marker xc0.sa8e-sa4e sic2.sics2-0=000 bit 4 marked transmit clocking e1 8mhz rev.1.0 1) only falling edge mode shown 2) delay t is programmable by xc0/1; sypx t 2) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 bit 4 marked dlx sa-bit marker xc0.sa8e-sa4e sic2.sics2-0=000 xdi/xsig sic2.sics2-0=001 xsigm time-slot marker xtr1...4 sic2.sics2-0=000
peb 22554 functional description e1 semiconductor group 58 09.98 transmit signaling controller similar to the receive signaling controller the same signaling methods and the same time-slot assignment is provided. the quadfalc will perform the following signaling and data link methods: ? hdlc or lapd access the transmit signaling controller of the quadfalc performs the flag generation, crc generation, zero bit-stuffing and programmable idle code generation. buffering of transmit data is done in the 64 byte deep xfifo. the signaling information will be internally multiplexed with the data applied to port xdi or xsig. in signaling controller transparent mode, fully transparent data transmission without hdlc framing is performed. optionally the quadfalc supports the continuous transmission of the xfifo contents. the quadfalc offers the flexibility to insert data during certain time-slots. any combinations of time-slots may be programmed separately for the receive and transmit directions. ? s a bit access the quadfalc supports the s a bit signaling of time-slot 0 of every other frame as follows: - the access via registers xsw - the access via registers xsa8-4, capable of storing the information for a complete multiframe - the access via the 64 byte deep xfifo of the signaling controller. this s a bit access gives the opportunity to transparent a bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. any combination of s a bits which should be inserted in the outgoing data stream may be selected by xc0.sa8-4. ? channel associated signaling cas transmit data stored in registers xs1-16 will transmitted on a multiframe boundary in time-slot 16. the signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side via pinfunction xsig, which is selected by register pc1-4. in external signaling mode the signaling data is received at port xsig. the signaling data is sampled with the working clock of the transmit system interface (sclkx) in conjunction with the transmit synchron. pulse (sypx ). data on xsig will be latched in the bit positions 5-8 per time-slot, bits 1-4 will be ignored. time-slot 0 and 16 are sampled completly (bit 1-8). the received cas multiframe will be inserted frame aligned into the data stream on xdi. data sourced by the internal signaling controller will overwrite the external signaling data. if the quadfalc is optioned for no signaling, the data stream from the system interface will pass the quadfalc undisturbed.
peb 22554 functional description e1 semiconductor group 59 09.98 transmit elastic buffer the received bit stream from pin xdi is optionally stored in the transmit elastic buffer. the memory is organized as the receive elastic buffer. the functions are also equal to the receive side. programming of the transmit buffer size is done by sic1.xbs1/0 : ? xbs1/0 = 00 : bypass of the transmit elastic buffer ? xbs1/0 = 01 : one frame buffer or 256 bits max. wander amplitude (peak-to-peak): 94 ui (1 ui = 488 ns ) average delay after performing a slip: 128 bits ? xbs1/0 = 10 : two frame buffer or 512 bits maximum of wander amplitude: 190 ui average delay after performing a slip: 1 frame or 256 bits ? xbs1/0 = 11 : short buffer or 92 bits : max. wander amplitude: 18 usec average delay after performing a slip: 46 bits the functions of the transmit buffer are: ? clock adaption between system clock (sclkx) and internally generated transmit route clock (xclk). ? compensation of input wander and jitter. ? frame alignment between system frame and transmit route frame ? reporting and controlling of slips writing of received data from xdi is controlled by sclkx/r and sypx / xmfs in conjunction with the programmed offset values for the transmit time-slot/clock-slot counters. reading of stored data is controlled by the clock generated by dco-x circuitry or the externally generated tclk and the transmit framer. with the dejittered clock data is read from the transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is done according to the receive direction. positive / negative slips are reported in interrupt status bits isr4.xsp and isr4.xsn. if the transmit buffer is bypassed data is directly transfered to the transmitter. the following table gives an overview of the transmit buffer operating modes. buffer size ts offset program. slip perform. bypass enabled no short buffer enabled yes 1 frame enabled yes 2 frames enabled yes
peb 22554 functional description e1 semiconductor group 60 09.98 transmitter the serial bit stream is then processed by the transmitter which has the following functions: ? frame/multiframe synthesis of one of the two selectable framing formats ? insertion of service and data link information ? ais generation (alarm indication signal) ? remote alarm generation ? crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error ? idle code generation per ds0 the frame / multiframe boundries of the transmitter may be externally synchronized by using the sypx / xmfs pin. any change of the transmit time-slot assignment will subsequently produce a change of the framing bit positions on the line side. this feature is required if signaling- and service- bits are routed through the switching network and are inserted in transmit direction via the system interface. in loop-timed configuration (lim2.elt) disconnecting the control of the transmit system highway from the transmitter is done by setting xsw.xtm. the transmitter is now in a free running mode without any possibility to actualize the multiframe position in case of changing the transmit time-slot assignment. the framing bits are generated independent of the transmit system interface. for proper operation the transmit elastic buffer size should be programmed to 2 frames. the contents of selectable time-slots can be overwritten by the pattern defined via register idle. the selection of idle channels is done by programming the four-byte registers icb1 icb4.
peb 22554 functional description e1 semiconductor group 61 09.98 transmit line interface the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by the digital transmitter. figure 22 transmitter configuration recommended transmitter configuration values similar to the receive line interface three different data types are supported: ? ternary signal single rail data is converted into a ternary signal which is output on pins xl1 and xl2. the hdb3 and ami line code is employed. selected by fmr0.xc1/0 and lim1.drs = 0. ? dual rail data pcm(+), pcm(C) at multifunction ports xdop/ xdon with 50 % or 100 % duty cycle and with programmable polarity. line coding is done in the same way as in the ternary interface. selected by fmr0.xc1/0 and lim1.drs = 1. ? unipolar data on port xoid will be transmitted either in nrz (non return to zero) with 100 % duty cycle or in cmi (code mark inversion or known as 1t2b) code with or without (fmr3.cmi) preprocessed hdb3 coding to a fibre optical interface. clocking off data is done with the rising edge of the transmit clock xclk (2048 khz) and with a programmable polarity. selection is done by fmr0.xc1 = 0 and lim1.drs = 1. parameter characteristic impedance [ w ] 120 75 r 1 ( 1 %) [ w ]7.57.5 t2 : t1 1 : 2.4 1 : 2.4 its10968 line t 1 t 2 xl2 xl1 r 1 1 r falc r
peb 22554 functional description e1 semiconductor group 62 09.98 programmable pulse shaper the analog transmitter includes a programmable pulse shaper to satisfy the requirements of itu-t i.431. the amplitude and shape of the transmit pulses are completely programmable via registers xpm0-2 from the microprocessor interface. the transmitter requires an external step up transformer to drive the line. transmit line monitor the transmit line monitor compares the transmit line current on xl1 and xl2 with an on-chip transmit line current limiter. the monitor detects faults on the primary side of the transformer indicated by a highly increased transmit line current (more than 120 ma for at least 3 pulses) and protects the device from damage by setting the transmit line driver xl1/2 automatically in a high impedance state. two conditions will be detected by the monitor: transmit line ones density (more than 31 consecutive zeros) indicated by frs1.xlo and transmit line high currrent indicated by frs1.xls. in both cases a transmit line monitor status change interrupt will be provided. figure 23 transmit line monitor configuration its10936 pulse shaper monitor line tri xdata xl1 xl2
peb 22554 functional description e1 semiconductor group 63 09.98 3.7 framer operating modes e1 general bit: fmr1.pmod = 0 pcm line bit rate : 2.048 mbit/s single frame length : 256 bit, no. 1 256 framing frequency : 8 khz hdlc controller : nx64 kbit/s , n = 1 ... 32 or nx4 kbit/s , n=1 ... 5 organization : 32 time-slots, no. 0 31 with 8 bits each, no. 1 8 the operating mode of the quadfalc is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the quadfalc implements all of the standard framing structures for e1 or pcm 30 (cept, 2.048 mbit/s) carriers. the internal hdlc- or cas controller supports all signaling procedures including signaling frame synchronization / synthesis and signaling alarm detection in all framing formats. the time-slot assignment from the pcm line to the system highway and vv. is performed without any changes of numbering (ts0 ? ts0, , ts31 ? ts31). summary of e1- framing modes ? doubleframe format according to itu-t g. 704 ? multiframe format according to itu-t g. 704 crc4 processing according to itu-t g. 706 ? multiframe format with crc4 to non crc4 interworking according to itu-t g. 706 ? multiframe format with modified crc4 to non crc4 interworking ? multiframe format with crc4 performance monitoring after reset, the quadfalc is switched into doubleframe format automatically. switching between the framing formats is done via bit fmr2.rfs1/0 and fmr3.extiw for the receiver and fmr1.xfs for the transmitter.
peb 22554 functional description e1 semiconductor group 64 09.98 3.7.1 doubleframe format the framing structure is defined by the contents of time-slot 0 (refer to table 6 ). table 6 allocation of bits 1 to 8 of time-slot 0 note: 1. s i bits: reserved for international use. if not used, these bits should be fixed to 1. access to received information via bits rsw.rsi and rsp.rsif. transmission is enabled via bits xsw.xsis and xsp.xsif. 2. fixed to 1. used for synchronization. 3. remote alarm indication: in undisturbed operation 0; in alarm condition 1. 4. s a bits: reserved for national use. if not used, they should be fixed at 1. access to received information via bits rsw.ry0 ry4. transmission is enabled via bits xsw.xy0 xy4. hdlc-signaling in bits sa4- sa8 is selectable. (*) note: (*) as a special extension for double frame format, the s a -bit registers rsa4-8 / xsa4-8 may be used optionally. bit alternate number frames 12 345678 frame containing the frame alignment signal s i 0 011011 note 1 frame alignment signal frame not containing the frame alignment signal or service word s i 1as a4 s a5 s a6 s a7 s a8 note 1 note 2 note 3 note 4
peb 22554 functional description e1 semiconductor group 65 09.98 transmit transparent modes in transmit direction, contents of time-slot 0 frame alignment signal of the outgoing pcm frame are normally generated by the quadfalc. however, transparency for the complete time-slot 0 can be achieved by selecting the transparent mode xsp.tt0. with the transparent service word mask register tswm the si-bits, a-bit and the sa4-8 bits can be selectively switched through transparently. synchronization procedure synchronization status is reported via bit frs0.lfa. framing errors are counted by the framing error counter (fec). asynchronous state is reached after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (bit 2 = 0 in time-slot 0 of every other frame not containing the frame alignment word), the selection is done via bit rc1.asy4. additionally, the service word condition can be disabled. when the framer lost its synchronization an interrupt status bit isr2.lfa is generated. in asynchronous state, counting of framing errors and detection of remote alarm will be stopped. ais is automatically sent to the backplane interface (can be disabled via bit fmr2.dais). further on the updating of the registers rsw, rsp, rsa4-8, rsa6s and rs1-16 will be halted (remote alarm indication, sa/si-bit access). the resynchronization procedure starts automatically after reaching the asynchronous state. additionally, it may be invoked user controlled via bit: fmr0.frs (force resynchronization: the fas word detection is interrupted until the framer is in the asynchronous state. after that, resynchronization starts automatically). synchronous state is established after detecting: C a correct fas word in frame n, C the presence of the correct service word (bit 2 = 1) in frame n + 1, 1) pin xdi or xsig or xfifo-buffer (signaling controller) 2) additionally, automatic transmission of the a-bit is selectable 3) as a special extension for double frame format, the sa-bit register may be used optionally . transmit transparent source for enabled by framing a bit s a bits s i bits C xsp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa4-8 (int. generated) via pin xdi 1) (int. generated) (int. generated) (int. generated) (int. generated) xsw.xra 2) via pin xdi xsw.xra xsw.xra via pin xdi xsw.xra xsw.xy0 4 3) via pin xdi xsw.xy0 4 xsw.xy0 4 xsw.xy0 4 via pin xdi xsw.xsis, xsp.xsif via pin xdi via pin xdi via pin xdi xsw.xsis, xsp.xsif xsw.xsis, xsp.xsif
peb 22554 functional description e1 semiconductor group 66 09.98 C a correct fas word in frame n + 2. if the service word in frame n + 1 or the fas word in frame n + 2 or both are not found searching for the next fas word will be start in frame n + 2 just after the previous frame alignment signal. reaching the synchronous state causes a frame alignment recovery interrupt status isr2.far if enabled. undisturbed operation starts with the beginning of the next doubleframe. a-bit access if the quadfalc detects a remote alarm indication in the received data stream the interrupt status bit isr2.ra will be set. with setting of bit xsw.xra a remote alarm (rai) will be send to the far end. by setting fmr2.axra the quadfalc automatically transmit the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment frs0.lfa = 1. if the receiver is in synchronous state frs0.lfa = 0 the remote alarm bit will be reset. note: the a-bit may be processed via the system interface. setting bit tswm.tra enables transparency for the a bit in transmit direction (refer to table 7 ). s a - bit access as an extension for access to the s a -bits via registers rsa4-8/xsa4-8 an option is implemented to allow the usage of internal s a -bit registers rsa4-8/xsa4-8 in doubleframe format. this function is enabled by setting fmr1.ensa = 1 for the transmitter and fmr1.rfs1/0 = 01 for the receiver. the quadfalc works then internally with a 16-frame structure but no crc multiframe alignment/generation is performed. 3.7.2 crc-multiframe the multiframe structure shown in table 7 is enabled by setting bit: fmr1.rfs1/0 for the receiver and fmr1.xfs for the transmitter. multiframe : 2 submultiframes = 2 8 frames frame alignment : refer to section doubleframe format multiframe alignment : bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern 001011 crc bits : bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14 crc block size : 2048 bit (length of a submultiframe) crc procedure : crc4, according to itu-t rec. g.704, g.706
peb 22554 functional description e1 semiconductor group 67 09.98 table 7 crc-multiframe structure e: spare bits for international use. access to received information via bits rsp.rs13 and rsp.rs15. transmission is enabled via bits xsp.xs13 and xsp.xs15. additionally, automatic transmission for submultiframe error indication is selectable. s a : spare bits for national use. additionally, sa bit access via registers rsa4 8 and xsa4 8 is provided. hdlc-signaling in bits sa4- sa8 is selectable. c 1 c 4 : cyclic redundancy check bits. a: remote alarm indication. additionally, automatic transmission of the a-bit is selectable. sub- multiframe frame number bits 1 to 8 of the frame 123456 78 multiframe i 0 1 2 3 4 5 6 7 c 1 0 c 2 0 c 3 1 c 4 0 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a4 1 s a4 1 s a4 1 s a4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a64 1 s a7 1 s a7 1 s a7 1 s a7 1 s a8 1 s a8 1 s a8 1 s a8 ii 8 9 10 11 12 13 14 15 c 1 1 c 2 1 c 3 e* c 4 e* 0 1 0 1 0 1 0 1 0 a 0 a 0 a 0 a 1 s a4 1 s a4 1 s a4 1 s a4 1 s a5 1 s a5 1 s a5 1 s a5 0 s a61 0 s a62 0 s a63 0 s a64 1 s a7 1 s a7 1 s a7 1 s a7 1 s a8 1 s a8 1 s a8 1 s a8
peb 22554 functional description e1 semiconductor group 68 09.98 for transmit direction, contents of time-slot 0 are additionally determined by the selected transparent mode: the crc procedure is automatically invoked when the multiframe structure is enabled. crc errors in the received data stream are counted by the 16 bit crc error counter cec (one error per submultiframe, maximum). additionally a crc4 error interrupt status isr0.crc4 may be generated if enabled by imr0.crc4. all crc bits of one outgoing submultiframe are automatically inverted in case a crc error is flagged for the previous received submultiframe. this function is enabled via bit rc0.crci. setting the bit rc0.xcrci will invert the crc bits before transmission to the distant end. the function of rc0.xcrci and rc0.crci are logically ored. synchronization procedure multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged at status bits frs0.lfa and frs0.lmfa). the rising edge of these bits will cause an interrupt status bits isr2.lfa + isr2.lmfa. the multiframe resynchronization procedure starts when doubleframe alignment has been regained which is indicated by an interrupt status bit isr2.far. for doubleframe synchronization refer to section doubleframe format. it may also be invoked by the user by setting C bit fmr0.frs for complete doubleframe and multiframe re-synchronization C bit fmr1.mfcs for multiframe re-synchronization only. 1) pin xdi or xsig or xfifo buffer (signaling controller) 2) automatic transmission of the a-bit is selectable 3) the s a -bit register xsa4-8 may be used optionally 4) additionally, automatic transmission of submultiframe error indication is selectable transmit transparent source for enabled by framing + crc a bit sa bits e bits C xsp.tt0 tswm.tsif tswm.tsis tswm.tra tswm.tsa4C8 (int. generated) via pin xdi 1) (int. generated) (int. generated) (int. generated) (int. generated) xsw.xra 2) via pin xdi xsw.xra 1) xsw.xra 1) via pin xdi xsw.xra 1) xsw.xy0 4 3) via pin xdi xsw.xy0 4 2) xsw.xy0 4 2) xsw.xy0 4 2) via pin xdi xsp.xs13/xs15 4) via pin xdi (int. generated) via pin xdi xsp.xs13/xs15 3) xsp.xs13/xs15 3)
peb 22554 functional description e1 semiconductor group 69 09.98 the crc checking mechanism will be enabled after the first correct multiframe pattern has been found. however, crc errors will not be counted in asynchronous state. in doubleframe asynchronous state, counting of framing errors, crc4 bit errors and detection of remote alarm will be stopped. ais is automatically sent to the backplane interface (can be disabled via bit fmr2.dais). further on the updating of the registers rsw, rsp, rsa4-8, rsa6s and rs1-16 will be halted (remote alarm indication, sa/si-bit access). the multiframe synchronous state is established after detecting two correct multiframe alignment signals at an interval of n 2 ms (n = 1, 2, 3 ). the loss of multiframe alignment flag frs0.lmfa will be reset. additionally an interrupt status multiframe alignment recovery bit isr2.mfar is generated with the falling edge of bit frs0.lmfa. automatic force resynchronization in addition, a search for doubleframe alignment is automatically initiated if two multiframe pattern with a distance of n 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained (bit fmr1.afr). a new search for frame alignment will be started just after the previous frame alignment signal. floating multiframe alignment window after reaching doubleframe synchronization a 8 ms timer is started. if a multiframe alignment signal is found during the 8 ms time interval the internal timer will be reset to remaining 6 ms in order to find the next multiframe signal within this time. if the multiframe signal is not found for a second time an interrupt status isr0. t8ms will be provided. this interrupt will usually occur every 8 ms until multiframe synchronization is achieved. crc4 performance monitoring in the synchronous state checking of multiframe pattern is disabled. however, with bit fmr2.almf an automatic multiframe resynchronization mode can be activated. if 915 out of 1000 errored crc submultiframes are found then a false frame alignment will be assumed and a search for double- and multiframe pattern is initiated. the new search for frame alignment will be started just after the previous basic frame alignment signal. the internal crc4 resynchronization counter will be reset when the multiframe synchronization has been regained. modified crc4 multiframe alignment algorithm the modified crc4 multiframe alignment algorithm allows an automatic interworking between framers with and without a crc4 capability. the interworking is realized as it is described in itu-t g.706 appendix b.
peb 22554 functional description e1 semiconductor group 70 09.98 if doubleframe synchronization is consistently present but crc4 multiframe alignment is not achieved within 400 ms it is assumed that the distant end is initialized to doubleframe format. the crc4 - non crc4 interworking is enabled via fmr2.rfs1/0 = 11 and is activated only if the receiver has lost its synchronization. if doubleframe alignment (basic frame alignment) is established a 400 ms timer and searching for multiframe alignment will be started. a research for basic frame alignment will be initiated if the crc4 multiframe synchronization could not be achieved within 8 ms and will be started just after the previous frame alignment signal. the research of the basic frame alignment is done in parallel and is independent of the synchronization procedure of the primary basic frame alignment signal. during the parallel search all receiver functions are based on the primary frame alignment signal, like framing errors, sa-, si-, a-bits ). all subsequent multiframe searches are associated with each basic framing sequence found during the parallel search. if the crc4 multiframe alignment sequence was not found within the time interval of 400 ms, the receiver will be switched into a non crc4 mode indicated by setting the bit frs0.nmf (no multiframing found) and isr2.t400ms. in this mode checking of crc bits is disabled and the received e-bits are forced to low. the transmitter framing format will not be changed. even if multiple basic fas resynchronizations have been established during the parallel search, the receiver will be maintained to the initially determined primary frame alignment signal location. however, if the crc4 multiframe alignment could be achieved within the 400 ms time interval assuming a crc4 to crc4 interworking, then the basic frame alignment sequence associated to the crc4 multiframe alignment signal will be chosen. if necessary, the primary frame alignment signal location will be adjusted according to the multiframe alignment signal. the crc4 performance monitoring will be started if enabled by fmr2.almf and the received e-bits will be processed in accordance with itu-t g.704. switching into the doubleframe format (non crc4) mode after 400 msec can be disabled by setting of fmr3.extiw. in this mode the quadfalc continues search for multiframing. in the interworking mode setting of bit fmr1.afr is not allowed. a-bit access if the quadfalc detects a remote alarm indication (bit 2 in ts0 not containing the fas word) in the received data stream the interrupt status bit isr2.ra will be set. with the deactivation of the remote alarm the interrupt status bit isr2.rar is generated. by setting fmr2.axra the quadfalc automatically transmits the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment (frs0.lfa = 1). if the receiver is in synchronous state (frs0.lfa = 0) the remote alarm bit will be reset in the outgoing data stream.
peb 22554 functional description e1 semiconductor group 71 09.98 additionally, if bit fmr3.extiw is set and the multiframesynchronous state could not be achieved within the 400 msec after finding the primary basic framing, the a-bit will be transmitted active high to the remote end until the multiframing is found. note: the a-bit may be processed via the system interface. setting bit tswm.tra enables transparency for the a bit in transmit direction (refer to table 7 ). s a - bit access due to signaling procedures using the five s a bits (s a4 s a8 ) of every other frame of the crc multiframe structure, three possibilities of access via the microprocessor are implemented. ? the standard procedure allows reading/writing the s a -bit registers rsw, xsw without further support. the s a -bit information will be updated every other frame. ? the advanced procedure, enabled via bit fmr1.ensa, allows reading/writing the s a -bit registers rsa4 8, xsa4 8. a transmit or receive multiframe begin interrupt (isr0.rmb or isr1.xmb) is provided. registers rsa4-8 contains the service word information of the previously received crc-multiframe or 8 doubleframes (bitslots 4-8 of every service word). these registers will be updated with every multiframe begin interrupt isr0.rmb. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of this registers xsa4-8 will be copied into shadow registers. the contents will subsequently sent out in the service words of the next outgoing crc multiframe (or every doubleframes) if none of the time-slot 0 transparent modes is enabled. the transmit multiframe begin interrupt xmb request that these registers should be serviced. if requests for new information will be ignored, current contents will be repeated. ? the extended access via the receive and transmit fifos of the signaling controller. in this mode it is possible to transmit / receive a hdlc frame or a transparent bit stream in any combination of the s a bits. enabling is done by setting of bit ccr1.eits and the corresponding bits xc0.sa8e-4e / tswm.tsa8-4 and resetting of registers ttr1-4, rtr1-4 and fmr1.ensa. the access to and from the fifos is supported by isr0.rme,rpf and isr1.xpr,als. C sa6-bit detection according to ets 300233 four consecutive received sa6-bits are checked on the by ets 300233 defined sa6-bit combinations. the quadfalc will detect following fixed sa6-bit combinations: sa61,sa62,sa63,sa64 = 1000; 1010; 1100; 1110; 1111. all other possible 4 bit combinations are grouped to status x. a valid sa6-bit combination must occur three times in a row. the corresponding status bit in register rsa6s will be set. register rsa6s is from type clear on read. with any
peb 22554 functional description e1 semiconductor group 72 09.98 change of state of the sa6-bit combinations an interrupt status isr0.sa6sc will be generated. during the basicframe asynchronous state updating of register rsa6s and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the sa6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6sy). in synchronous detection mode updating of register rsa6s is done in the multiframe synch. state (frs0.lmfa=0). in asynchr. detection mode updating is independent to the multiframe synchronous state. C sa6 bit error indication counters the sa6 bit error indication counter crc2l/h (16 bits) counts the received sa6 bit sequence 0001 or 0011 in every crc submultiframe.in the primary rate access digital section this counter option gives information about crc errors reported from the te via sa6 bit. incrementing is only possible in the multiframe synchronous state. the sa6 bit error indication counter crc3l/h (16 bits) counts the received sa6 bit sequence 0010 or 0011 in every crc submultiframe. in the primary rate access digital section this counter option gives information about crc errors detected at t-reference point and reporting them via the sa6 bit. incrementing is only possible in the multiframe synchronous state.
peb 22554 functional description e1 semiconductor group 73 09.98 e-bit access due to signaling requirements, the e bits of frame 13 and frame 15 of the crc multiframe can be used to indicate received errored submultiframes: submultiframe i status e- bit located in frame 13 submultiframe ii status e- bit located in frame 15 no crc error: : e = 1 crc error: : e = 0 C standard procedure after reading the submultiframe error indication rsp.si1 and rsp.si2, the microprocessor has to update contents of register xsp (xs13, xs15). access to these registers has to be synchronized to transmit or receive multiframe begin interrupts (isr0.rmb or isr1.xmb). C automatic mode by setting bit xsp.axs status information of received submultiframes is automatically inserted in e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. in the double- and multiframe asynchronous state the e-bits are set to zero. however they can be set to one in the async. state if enabled by bit xsp.ebp. in the multiframe sync. state the e-bits are processed according to itu-t g.704 independent of bit xsp.ebp C submultiframe error indication counter the ebc (e-bit) counter ebcl and ebch (16 bits) counts zeros in e-bit position of frame 13 and 15 of every received crc multiframe. this counter option gives information about the outgoing transmit pcm line if the e bits are used by the remote end for submultiframe error indication. incrementing is only possible in the multiframe synchronous state. note: e-bits may be processed via the system interface. setting bit tswm.tsis enables transparency for e bits in transmit direction (refer to table 7 ).
peb 22554 functional description e1 semiconductor group 74 09.98 figure 24 crc4 multiframe alignment recovery algorithms (bfa = basic frame alignment) itd10310 out of primary bfa: inhibit incoming crc-4 performance monitoring reset all timers set frs0.lfa/lmfa/nmf = 110 no bfa search ? primary yes reset internal frame alignment status start 400 ms timer in primary bfa: enable primary bfa loss checking process (frs0.lfa = 0) start 8 ms timer can crc-4 mfa be found yes in 8 ms ? 400 ms timer elapsed ? yes no parallel bfa search good ? no no assume crc-4 to crc-4 interworking: confirm primary bfa associated with crc-4 mfa reset internal multiframe alignment status adjust primary bfa if necessary (frs0.lmfa = 0) confirm primary bfa set internal 400 ms timer expiration status bit assume crc-4 to non crc-4 interworking: (frs0.nmf = 1) start crc-4 performance monitoring yes or lfa ? error count crc-4 no continue crc-4 performance monitoring _ < 915 yes crc-4 mfa search
peb 22554 functional description e1 semiconductor group 75 09.98 3.7.3 additional functions error performance monitoring and alarm handling ? alarm detection and generation alarm indication signal: detection and recovery is flagged by bit frs0.ais and isr2.ais. transmission is enabled via bit fmr1.xais. loss of signal: detection and recovery is flagged by bit frs0.los and isr2.los. remote alarm indication: detection and release is flagged by bit frs0.rra, rsw.rra and isr2.ra/rar. transmission is enabled via bit xsw.xra. ais in time-slot 16: detection and release is flagged by bit frs1.ts16ais and isr3.ais16. transmission is enabled by writing all ones in registers xs1-16. los in time-slot 16: detection and release is flagged by bit frs1.ts16los. transmission is enabled by writing all zeros in registers xs1-16. remote alarm in time-slot 16: detection and release is flagged by bit frs1.ts16ra and isr3.ra16. transmission is enabled via bit ccr1.xts16ra or xs1.2 . transmit line shorted: detection and release is flagged by bit frs1.xls and isr1.xlsc. transmit ones density: detection and release is flagged by bit frs1.xlo and isr1.xlsc.
peb 22554 functional description e1 semiconductor group 76 09.98 table 8 summary of alarm detection and release alarm detection condition clear condition loss of signal (los) no transitions (logical zeros) in a programmable time interval of 16 - 4096 consecutive pulse periods. programmable receive input signal threshold programmble number of ones (1-256) in a programmable time interval of 16 - 4096 consecutive pulse periods. a one is a signal with a level above the programmed threshold. alarm indication signal (ais) fmr0.alm = 0: less than 3 zeros in 250 sec and loss of frame alignment declared fmr0.alm = 1: less than 3 zeros in each of two consecutive 250 sec periods fmr0.alm = 0: more than 2 zeros in 250 sec fmr0.alm = 1: more than 2 zeros in each of two 500 sec periods remote alarm (rra) bit 3 = 1 in time-slot 0 not containing the fas word set conditions no longer detected. remote alarm in time-slot 16 (ts16ra) y-bit = 1 received in cas multiframe alignment word y-bit = 0 received in cas multiframe alignment word loss of signal in time-slot 16 (ts16los) all zeros for at least 16 consecutively received time-slots 16 receiving a one in time-slot 16 alarm indication signal in time-slot 16 (ts16ais) time-slot 16 containing less than 4 zeros in each of two consecutive cas multiframes periods time-slot 16 containing more than 3 zeros in each of two consecutive cas multiframes periods transmit line short (xls) more than 32 pulse periods with highly increased transmit line current on xl1/2 no transmit line current limiter active transmit ones density (xlo) 32 consecutive zeros in the transmit data stream on xl1/2 cleared with each transmitted pulse
peb 22554 functional description e1 semiconductor group 77 09.98 ? auto modes - automatic remote alarm access if the receiver has lost its synchronization a remote alarm could be sent automatically, if enabled by bit fmr2.axra to the distant end. the remote alarm bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be removed. - automatic e bit access by setting bit xsp.axs status information of received submultiframes is automatically inserted in e-bit position of the outgoing crc multiframe without any further interventions of the microprocessor. - automatic ais to system interface in asynchronous state the synchronizer enforces automatically an ais to the receive system interface. however, received data can be transparently switched through if bit fmr2.dais is set. - automatic clock source switching in slave mode (lim0.mas = 0) the dco-r will synchronize to the recovered route clock. in case of loss of signal los the dco-r switches automatically to master mode. if bit cmr1.dcs is set automatic switching from rclk to sync may be disabled. - automatic freeze signaling: updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss of signal, or a loss of cas multiframe alignment or a receive slip occures. the internal signaling buffer rs1-16 is frozen. optionally automatic freeze signaling may be disabled by setting bit sic3.daf. ? error counter the quadfalc offers six error counters each of them has a length of 16 bit. they record code violations, framing bit errors, crc4 bit errors and crc4 error events which are flagged in the different sa6 bit combinations or the number of received multiframes in the asynchronous state or the change of frame alignment (cofa). counting of the multiframes in the asyn. state and the cofa parameter is done in a 6 / 2 bit counter and is shared with cec3l/h. each of the error counter is buffered. updating the buffer is done in two modes: - one second accumulation - on demand via handshake with writing to the dec register in the one second mode an internal/external one second timer will update these buffers and reset the counter to accumulate the error events in the next one second period. the error counter can not overflow. error events occuring during reset will not lost. ? status : errored second the quadfalc supports the error performance monitoring by detecting the following alarms or error events in the received data: framing errors , crc errors , code violations , loss of frame alignment , loss of signal,
peb 22554 functional description e1 semiconductor group 78 09.98 alarm indication signal , e bit error , receive and transmit slips. with a programmable interrupt mask register esm all these alarms or error events could generate an errored second interrupt (isr3.es) if enabled. ? second timer additionally per channel a one second timer interrupt could be internally generated to indicate that the enabled alarm status bits or the error counters have to be checked. if enabled via bit gpc1.fss2-0 the one second timer of the selected channel can be output on port sec/fsc (gpc1.csfp1/0). optionally if all four channels of the quadfalc should synchronized to an external second timer an appropriate clock has to be provided to pin sec/fsc. selecting the external second timer is done with gcr.ses. refer also to register gpc1. in-band loop generation and detection the quadfalc generates and detects a framed or unframed in-band loop up/actuate - and down/deactuate pattern with bit error rates as high as 1/100. framed or unframed in-band loop code is selected by lcr1.fllb . replacing transmit data with the in-band loop codes is done by fmr3.xld / xlu. the quadfalc also offers the ability generating and detecting of a flexible in-band loop up - and down pattern (lcr1.llbp = 1). the loop up and loop down pattern is individual programmable from 2 to 8 bit in length (lcr1.lac1/0 and lcr1.ldc1/0). programming of loop codes is done in registers lcr2 and lcr3. status and interrupt-status bits will inform the user whether loop up - or loop down code was detected. time-slot 0 transparent mode the transparent modes are useful for loopbacks or for routing data unchanged through the quadfalc. in receive direction, transparency for ternary or dual / single rail unipolar data is always achieved if the receiver is in the synchronous state. in asynchronous state the data may be transparently switched through if bit fmr2.dais is set. however, correct time-slot assignment can not be guaranteed due to missing frame alignment between line and system side. setting of bit fmr2.rtm disconnects control of the internal elastic store from the receiver. the elastic buffer is now in a free running mode without any possibility to actualize the time slot assignment to a new frame position in case of re-synchronization of the receiver. together with fmr2.dais this function can be used to realize undisturbed transparent reception. transparency in transmit direction can be achieved by activating the time-slot 0 transparent mode (bit xsp.tt0 or tswm.7-0). if xsp.tt0 = 1 all internal information of
peb 22554 functional description e1 semiconductor group 79 09.98 the quadfalc (framing, crc, sa/si bit signaling, remote alarm) will be ignored. with register tswm the si-bits, a-bit or the sa4-8 bits could be selectively enabled to send data transparent from port xdi to the far end. for complete transparency the internal signaling controller, idle code generation and ais alarm generation, single channel and payload loop back has to be disabled. pseudo-random bit sequence generation and monitor the quadfalc has the added ability to generate and monitor 2 15 -1 and 2 20 -1 pseudo- random bit sequences (prbs). the generated prbs pattern will be transmitted optionally inverted or not to the remote end via pins xl1/2 resp. xdop/n. generating and monitoring of prbs pattern is done according to itu-t o. 151. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error will increment an error counter (cec2). synchronization will be reached within 400 msec with a probability of 99.9% and a ber of 1/10.
peb 22554 functional description e1 semiconductor group 80 09.98 single channel loop back each of the 32 time-slots may be selected for loopback from the system pcm input (xdi) to the system pcm output (rdo). this loopback is programmed for one time-slot at a time selected by register loop. during loopback, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route time-slot. for the time-slot test, sending sequences of test patterns like a 1 khz check signal should be avoided. otherwise, an increased occurrence of slips in the tested time-slot will disturb testing. these slips do not influence the other time-slots and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 25 single channel loopback its09747 rdo xdi rclk rl1 rl2 xl1 xl2 idle code framer trans. framer rec. store elast. store elast. mux mux recovery data clock +
peb 22554 functional description e1 semiconductor group 81 09.98 payload loop back to perform an effective circuit test a payload loop is implemented. the payload loop back (fmr2.plb) will loop the data stream from the receiver section back to transmitter section. the looped data will pass the complete receiver including the wander and jitter compensation in the receive elastic store and were output on pin rdo. instead of the data an ais (fmr2.sais) could be sent to the system interface. the framing bits, crc4 and spare bits are not looped, if xsp.tt0 =0. they are originated by the quadfalc transmitter. if the plb is enabled the transmitter and the data on pins xl1/2 or xdop/xdon are clocked with sclkr instead of sclkx. if xsp.tt0 = 1 the received time-slot 0 is sent transparently back to the line interface. data on the following pins are ignored: xdi, xsig, tclk, sclkx, sypx and xmfs. all the received data is processed normally. figure 26 payload loop its09748 clock + data rec. framer elast. store trans. framer rdo xdi rclk rl1 rl2 xl1 xl2 recovery sclkx sclkr mux ais-gen elast. store
peb 22554 functional description e1 semiconductor group 82 09.98 local loop the local loopback mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. however, the bit stream will be undisturbed transmitted on the line. however an ais to the distant end could be enabled by setting fmr1.xais without influencing the data looped back to the system interface. note that enabling the local loop will usually invoke an out of frame error until the receiver can resync to the new framing. the serial code from the transmitter and receiver has to be programmed identically. figure 27 local loop its09749 rdo xdi rclk ais-gen rl1 rl2 xl1 xl2 framer rec. framer trans. store elast. recovery data clock + mux elast. store
peb 22554 functional description e1 semiconductor group 83 09.98 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs xl1/2 or xdop/xdon via the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loopback mode is selected by setting the respective control bits lim1.rl+jatt. received data may be looped with or without the transmit jitter attenuator (fifo). figure 28 remote loop its09750 rdo xdi rclk rl1 rl2 xl1 xl2 fifo xclk rclk dco1/2 framer rec. framer trans. store elast. elast. store recovery data clock + mux mux
peb 22554 functional description e1 semiconductor group 84 09.98 alarm simulation alarm simulation does not affect the normal operation of the device, i.e. all time-slots remain available for transmission. however, possible real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: ? loss of signal ? alarm indication signal (ais) ? loss of pulse frame ? remote alarm indication ? receive and transmit slip indication ? framing error counter ? code violation counter (hdb3 code) ? crc4 error counter ? e-bit error counter ? cec2 counter ? cec3 counter some of the above indications are only simulated if the quadfalc is configured in a mode where the alarm is applicable (e.g. no crc4 error simulation when doubleframe format is enabled). C setting of the bit fmr0.sim initiates alarm simulation, interrupt status bits will be set. error counting and indication will occurs while this bit is set. after it is reset all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. alarms like ais and los are cleared automatically. interrupt status register and error counters are automatically cleared on read.
peb 22554 operational description e1 semiconductor group 85 09.98 4 operational description e1 4.1 signaling controller operating modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 4 different operating modes which can be set via the mode register. 4.1.1 hdlc mode all frames with valid addresses are forwarded directly via the rfifo to the system memory. depending on the selected address mode, the quadfalc can perform a 1 or 2 byte address recognition (mode.mds0). if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) and will be excluded from the address comparison. similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the quadfalc can be called (addressed) with 6 different address combinations. hdlc frames with address fields that do not match any of the address combinations, are ignored by the falc. in case of a 1-byte address, ral1 and ral2 will be used as compare registers. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. additional information can also be read from a special register (rsis). as defined by the hdlc protocol, the quadfalc perform the zero bit insertion/deletion (bit-stuffing) in the transmit/receive data stream automatically. that means, it is guaranteed that at least after 5 consecutive 1-s a 0 will appear. non-auto-mode (mode.mds2-1=01) characteristics: address recognition, flag - and crc generation/check, bit-stuffing all frames with valid addresses are forwarded directly via the rfifo to the system memory. transparent mode 1 (mode.mds2-0=101) characteristics: address recognition, flag - and crc generation/check, bit-stuffing
peb 22554 operational description e1 semiconductor group 86 09.98 only the high byte of a 2-byte address field will be compared with registers rah1/2. the whole frame excluding the first address byte will be stored in rfifo. transparent mode 0 (mode.mds2-0=100) characteristics: flag - and crc generation/check, bit-stuffing no address recognition is performed and each frame will be stored in the rfifo. receive data flow the following figure gives an overview of the management of the received hdlc frames in the different operating modes. figure 29 receive data flow of quadfalc if ccr3 address optionally stored in rfifo crc optionally stored in rfifo if ccr3 the control field starts here! in case of on 8 bit address, ctrl stored (fifo, processed autonomously compared with (register) description of symbols: 10 register) transparent 00 note: 2) 1) mds2 10 01 mode 01 . transparent auto/8 1 0 non 1 auto/16 0 1 - non flag 2) rah1, 2 2) ral1, 2 x ral1, 2 rah1, 2) addr 2 2) "1". "1". radd . = rcrc . = rfifo 1) rsis itd06455 flag rfifo rfifo 1) rfifo i 1) rsis rsis rsis crc
peb 22554 operational description e1 semiconductor group 87 09.98 transmit data flow the frames can be transmitted as shown below. figure 30 transmit data flow of quadfalc transmitting a hdlc frame via register cmdr.xtf, the address, the control fields and the data field have to be entered in the xfifo. if ccr3.xcrc is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will be closed automatically only with a (closing) flag. the quadfalc does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 4.1.2 extended transparent mode characteristics: fully transparent in no hdlc mode, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, or bit- stuffing. this feature can be profitably used e.g for: ? specific protocol variations ? transmission of a bom frame ? test purposes data transmission is always performed out of the xfifo. in transparent mode, the receive data is shifted into the rfifo. control (xhf) frame hdlc transmit address flag xfifo addr ctrl flag data i checkram itd06456 crc
peb 22554 operational description e1 semiconductor group 88 09.98 4.1.3 signaling controller functions shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting bit sflg in control register ccr1. transparent transmission and reception when programmed in the extended transparent mode via the mode register (mds2- 0 = 111), the quadfalc performs fully transparent data transmission and reception without hdlc framing, i.e. without ? flag insertion and deletion ? crc generation and checking ? bit-stuffing in order to enable fully transparent data transfer, bit mode.hrac has to be set. received data is always shifted into rfifo. data transmission is always performed out of xfifo by directly shifting the contents of xfifo in the outgoing datastream. transmission is initiated by setting cmdr.xtf (04 h ). a synch-byte ff h is automatically sent before the first byte of the xfifo will be transmitted. cyclic transmission (fully transparent) if the extended transparent mode is selected, the quadfalc supports the continuous transmission of the contents of the transmit fifo. after having written 1 to 32 bytes to xfifo, the command xrep.xtf via the cmdr register (bit 7 ? 0 = 00100100 = 24 h ) forces the quadfalc to transmit the data stored in xfifo repeatedly to the remote end. note: the cyclic transmission continues until a reset command (cmdr: sres) is issued or with resetting cmdr.xrep, after which continuous 1-s are transmitted. during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. crc on/off features as an option in hdlc mode the internal handling of received and transmitted crc checksum can be influenced via control bits ccr3.rcrc and ccr3.xcrc. ? receive direction the received crc checksum is always assumed to be in the 2 (crc-itu) last bytes of a frame, immediately preceding a closing flag. if ccr3.rcrc is set, the received crc checksum will be written to rfifo where it precedes the frame status byte (contents of register rsis). the received crc checksum is additionally checked for
peb 22554 operational description e1 semiconductor group 89 09.98 correctness. if hdlc mode is selected, the limits for valid frame check are modified (refer to description of bit rsis.vfr). ? transmit direction if ccr3.xcrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will only be closed automatically with a (closing) flag. the quadfalc does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 4.1.3.1 hdlc data transmission in transmit direction 2x32 byte fifo buffers are provided. after checking the xfifo status by polling the bit sis.xfw or after an interrupt isr1.xpr (transmit pool ready), up to 32 bytes may be entered by the cpu to the xfifo. the transmission of a frame can be started by issuing a xtf or xhf command via the command register. if the transmit command does not include an end of message indication (cmdr.xme), the quadfalc will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per xme command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames may be share a flag, or may be transmitted as back-to-back frames, if service of xfifo is quick enough. in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt isr1.xdu. the frame may be aborted per software cmdr.sres.
peb 22554 operational description e1 semiconductor group 90 09.98 the data transmission sequence, from the cpus point of view, is outlined in figure 31 . figure 31 interrupt driven data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) shown in figure 32 . itd08565 start transmit pool ready ? xpr interrupt, xfw bit in sis register or =1 write data (up to 32 to xfifo bytes) y message end of ? xtf/xhf command n y n command xtf/xhf end + xme itd10971 wr xfifo 32 bytes system interface interface cpu alls xpr xhf + xme 6 bytes wr xfifo xpr xpr xhf 32 bytes wr xfifo command xhf transmit frame (70 bytes) 32 32 6 r falc
peb 22554 operational description e1 semiconductor group 91 09.98 figure 32 interrupt driven transmission example 4.1.3.2 hdlc data reception also 2 32 byte fifo buffers are provided in receive direction. there are different interrupt indications concerned with the reception of data: rpf (receive pool full) interrupt, indicating that a 32-byte-block of data can be read from rfifo and the received message is not yet complete. rme (receive message end) interrupt, indicating that the reception of one message is completed. the following figure gives an example of a reception sequence, assuming that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 33 interrupt driven reception sequence example itd10972 rd rfifo 32 bytes rmc receive frame 1 (66 bytes) 32 6 rpf rpf 32 2 32 bytes rd rfifo rmc rme rd status rd2 bytes rme rmc rd6 bytes rd status rmc rme rmc rd status rd6 bytes 6 rf2 rf3 falc r interface cpu interface system
peb 22554 operational description e1 semiconductor group 92 09.98 4.1.4 s a bit access the quadfalc supports the s a bit signaling of time-slot 0 of every other frame as follows: ? the access via registers rsw / xsw ? the access via registers rsa8-4 / xsa4-8 capable of storing the information for a complete multiframe ? the access via the 64 byte deep receive/transmit fifo of the integrated signaling controller. this s a bit access gives the opportunity to transmit/receive a transparent bit stream as well as hdlc frames where the signaling controller automatically processes the hdlc protocol. enabling is done by setting of bit ccr1.eits and resetting of registers ttr1-4, rtr1-4 and fmr1.ensa. the data written to the xfifo will subsequently transmit in the s a bit positions defined by register xc0.sa8e-4e and the corresponding bits of tswm.tsa8-4. any combination of s a bits can be selected. after the data have been completely sent out an all ones or flags (ccr1.itf) will be transmitted. the continuous transmission of a transparent bit stream, which is stored in the xfifo, can be enabled. with the setting of bit mode.hrac the received s a bits can be forwarded to the receive fifo. the access to and from the fifos is supported by isr0.rme/rpf and isr1.xpr/als. 4.2 operational phase the quadfalc is programmable via a microprocessor interface which enables byte or word access to all control and status registers. after reset the quadfalc must be first initialized. general guidelines for initialization are described in section initialization . the status registers are read-only and are continuously updated. normally, the processor periodically reads the status registers to analyze the alarm status and signaling data. reset the quadfalc is forced to the reset state if a high signal is input at port res for a minimum period of 10 m s. during reset the quadfalc needs an active clock on pin mclk. a ll output stages are in a high impedance state, all internal flip-flops are reset and most of the control registers are initialized with default values.
peb 22554 operational description e1 semiconductor group 93 09.98 after reset, the quadfalc is initialized for doubleframe format with register values listed in table 9 . table 9 initial values after reset register reset value meaning fmr0 00 h nrz coding, no alarm simulation. fmr1 fmr2 00 h pcm 30 C doubleframe format, 2 mbit/s system data rate, no ais transmission to remote end or system interface, payload loop off. sic1 sic2, sic3 00 h 00 h 00 h 8.192 mhz system clocking rate, rec. buffer 2 frames, transmit buffer bypass, data sampled or transmitted on the falling edge of sclkr/x, automatic freeze signaling, data is active in the first channel phase loop xsw xsp tswm 00 h 40 h 00 h 00 h channel loop back and single frame mode are disabled. all bits of the transmitted service word are cleared (bit 2 excl.). spare bit values are cleared. no transparent mode active. xc0 xc1 00 h 00 h the transmit clock offset is cleared. the transmit time-slot offset is cleared. rc0 rc1 00 h 00 h the receive clock slot offset is cleared. the receive time-slot offset is cleared. idle icb 1 4 00 h 00 h idle channel code is cleared. normal operation (no idle channel selected). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared xpm2-0 00 h, 03 h , 9c h transmit pulse mask imr0-4 ff h, ff h, ff h, ff h, ff h, all interrupts are disabled rtr1-4 ttr1-4 00 h, 00 h, 00 h, 00 h, no time-slots selected gcr 00 h internal second timer, power on of all 4 single falc channels, cmr1 00 h dco-r reference clock: channel 1, rclk output: dpll clock, dco-x enabled, dco-x internal reference clock
peb 22554 operational description e1 semiconductor group 94 09.98 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t and etsi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 10 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, may be programmed simultaneously. the bit fmr1.pmod should always be kept low. cmr2 00 h sclkr selected, sclkx selected, rec. synchr. pulse sourced by sypr , tr. synchr. pulse sourced by sypx , gpc1 00 h system multiplex mode disabled, sec port input active high, fsc is sourced by channel 1, rclk1 clock source: channel 1, pc1-4 00 h , 00 h 00 h , 00 h input function of ports rp(a-d) : sypr , input function of ports xp(a-d) : sypx pc5 00 h sclkr, sclkx, rclk configured to inputs, xmfs active low mode 00 h signaling controller disabled rah1/2 ral1/2 fd h , ff h ff h , ff h compare register for receive address cleared table 9 initial values after reset (contd) register reset value meaning
peb 22554 operational description e1 semiconductor group 95 09.98 features like channel loop back, idle channel activation, extensions for signaling support, alarm simulation, may be activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00 hex. all control registers (except xfifo, xs1-16, cmdr, dec) are of type: read/write. table 10 initialization parameters basic set up e1 mode select specification of line interface and clock generation line interface coding loss of signal detection/recovery conditions system clocking and data rate transmit offset counters receive offset counters ais to system interface fmr1.pmod = 0 lim0, lim1, xpm2-0 fmr0.xc1/0, fmr0.rc1/0 pcd, pcr, lim1, lim2 sic1.ssc1/0, sic1.ssd1,fmr1.ssd0 cmr2.irsp/irsc/ ixsp/ixsc xc0.xco, xc1.xto rc0.rco, rc1.rto fmr2.dais/sais operational set up e1 select framing framing additions synchronization mode signaling mode fmr2.rfs1/0, fmr1.xfs rc1.asy4, rc1.swd fmr1.afr, fmr2.almf xsp, xsw, fmr1.ensa, xsa8-4, tswm, mode, ccr1, ccr2, rah1/2, ral1/2
peb 22554 operational description e1 semiconductor group 96 09.98 4.3 specific e1 initialization the following is a suggestion for a basic initialization to meet most of the e1 requirements. depending on different applications and requirement any other initialization can be used. liu initialization framer initialization the selection of the following modes during the basic initialization supports the etsi requirements for e-bit access, remote alarm and synchronization (please refer also to quadfalc driver code of the evaluation system easy22554 and application notes) and helps to reduce the software load. they are very helpful especially to meet requirements as specified in ets300 011. fmr0.xc0/ fmr0.rc0/ lim1.drs fmr3.cmi the quadfalc supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami and hdb3 are supported. for the digital line interface modes (dual or single rail) the quadfalc supports ami, hdb3, cmi (with and without hdb3 precoding) and nrz. pcd = 0x0a los detection after 176 consecutive zeros (fulfills g.775 spec). pcr = 0x15 los recovery after 22 ones in the pcd intervall. (fulfills g.775). lim1.ril2-0 = 0x02 los threshold of 0.6 v (fulfills g.775). xsp.axs = 1 ets300 011 c4.x for instance requires the sending of e-bits in ts0 if crc4 errors have been detected. by programming xsp.axs = 1 the submultiframe status is inserted automatically in the next outgoing multiframe. xsp.ebp = 1 if the quadfalc has reached asynchronous state the e-bit is set to 0 if xsp.ebp = 0 and set to 1 if xsp.ebp = 1. ets300 011 requires that the e-bit is set to 1 in asynchronous state. fmr2.axra = 1 the transmission of rai via the line interface is done automatically by the quadfalc in case of loss of frame alignment (frs0.lfa = 1). if basic framing has been reinstalled rai is automatically reset. fmr2.frs1/2 = 10 fmr1.afr = 1 in this mode a search of double framing is automatically reinitiated if no crc4 multiframing could be found within 8ms. together with fmr2.axra = 1 this mode is essential to meet ets300 011 and reduces the processor load heavily.
peb 22554 operational description e1 semiconductor group 97 09.98 signaling controller initialization initialization of the hdlc controller: initialization of the cas-cc controller: after the device initialization a software reset should be executed by setting of bits cmdr.xres/rres. fmr2.almf = 1 the receiver initiates a new basic- and multiframing research if more than 914 crc4 errors have been detected in one second. fmr2.frs1/0 = 11 in the interworking mode the quadfalc stays in double framing format if no multiframe pattern could be found in a time intervall of 400 ms. this is also indicated by a 400 ms interrupt. additionally the extended interworking mode (fmr3.extiw = 1) will activate after 400 ms the remote alarm (fmr2.axra = 1) and will still search the multiframing without switching completely to the double framing. a complete resynchronization in an 8 ms interval is not initiated. mode = 0x88 hdlc receiver active, no address comparison. ccr1 = 0x18 enable signaling via ts0-31, interframe time fill with continous flags. imr0.rme = 0 imr0.rpf = 0 imr1.xpr = 0 unmask interrupts for hdlc processor requests. rtr3.ts16 = 1 xtr3.ts16 = 1 select ts16 for hdlc data reception and transmission. xsp.casen = 1 ccr1.eits = 0 send cas infos stored in the xs1-16 registers. imr0.casc = 0 enable interrupt with any data change in the rs1-16 registers.
peb 22554 operational description e1 semiconductor group 98 09.98 4.4 control register description table 11 control register address arrangement address register type comment 00 100 200 300 xfifo w transmit fifo 01 101 201 301 xfifo w transmit fifo 02 102 202 302 cmdr w command register 03 103 203 303 mode r/w mode register 04 104 204 304 rah1 r/w receive address high 1 05 105 205 305 rah2 r/w receive address high 2 06 106 206 306 ral1 r/w receive address low 1 07 107 207 307 ral2 r/w receive address low 2 08 ipc r/w interrupt port configuration 09 109 209 309 ccr1 r/w common configuration register 1 0a 10a 20a 30a ccr2 r/w common configuration register 2 0c 10c 20c 30c rtr1 r/w receive timeslot register 1 0d 10d 20d 30d rtr2 r/w receive timeslot register 2 0e 10e 20e 30e rtr3 r/w receive timeslot register 3 0f 10f 20f 30f rtr4 r/w receive timeslot register 4 10 110 210 310 ttr1 r/w transmit timeslot register 1 11 111 211 311 ttr2 r/w transmit timeslot register 2 12 112 212 312 ttr3 r/w transmit timeslot register 3 13 113 213 313 ttr4 r/w transmit timeslot register 4 14 114 214 314 imr0 r/w interrupt mask register 0 15 115 215 315 imr1 r/w interrupt mask register 1 16 116 216 316 imr2 r/w interrupt mask register 2 17 117 217 317 imr3 r/w interrupt mask register 3 18 118 218 318 imr4 r/w interrupt mask register 4 1c 11c 21c 31c fmr0 r/w framer mode register 0 1d 11d 21d 31d fmr1 r/w framer mode register 1 1e 11e 21e 31e fmr2 r/w framer mode register 2 1f 11f 21f 31f loop r/w channel loop back 20 120 220 320 xsw r/w transmit service word
peb 22554 operational description e1 semiconductor group 99 09.98 21 121 221 321 xsp r/w transmit spare bits 22 122 222 322 xc0 r/w transmit control 0 23 123 223 323 xc1 r/w transmit control 1 24 124 224 324 rc0 r/w receive control 0 25 125 225 325 rc1 r/w receive control 1 26 126 226 326 xpm0 r/w transmit pulse mask 0 27 127 227 327 xpm1 r/w transmit pulse mask 1 28 128 228 328 xpm2 r/w transmit pulse mask 2 29 129 229 329 tswm r/w transparent service word mask 2b 12b 22b 32b idle r/w idle channel code 2c 12c 22c 32c xsa4 r/w transmit sa4 bit register 2d 12d 22d 32d xsa5 r/w transmit sa5 bit register 2e 12e 22e 32e xsa6 r/w transmit sa6 bit register 2f 12f 22f 32f xsa7 r/w transmit sa7 bit register 30 130 230 330 xsa8 r/w transmit sa8 bit register 31 131 231 331 fmr3 r/w framer mode register 3 32 132 232 332 icb1 r/w idle channel register 1 33 133 233 333 icb2 r/w idle channel register 2 34 134 234 334 icb3 r/w idle channel register 3 35 135 235 335 icb4 r/w idle channel register 4 36 136 236 336 lim0 r/w line interface mode 0 37 137 237 337 lim1 r/w line interface mode 1 38 318 238 338 pcd r/w pulse count detection 39 139 239 339 pcr r/w pulse count recovery 3a 13a 23a 33a lim2 r/w line interface mode 2 3b 13b 23b 33b lcr1 r/w loop code register 1 3c 13c 23c 33c lcr2 r/w loop code register 2 3d 13d 23d 33d lcr3 r/w loop code register 3 3e 13e 23e 33e sic1 r/w system interface control 1 3f 13f 23f 33f sic2 r/w system interface control 2 table 11 control register address arrangement (contd) address register type comment
peb 22554 operational description e1 semiconductor group 100 09.98 40 140 240 340 sic3 r/w system interface control 3 44 144 244 344 cmr1 r/w clock mode register 1 45 145 245 345 cmr2 r/w clock mode register 2 46 146 246 346 gcr r/w global configuration register 47 147 247 347 esm r/w errored second mask 60 160 260 360 dec w disable error counter 70 170 270 370 xs1 w transmit cas register 1 71 171 271 371 xs2 w transmit cas register 2 72 172 272 372 xs3 w transmit cas register 3 73 173 273 373 xs4 w transmit cas register 4 74 174 274 374 xs5 w transmit cas register 5 75 175 275 375 xs6 w transmit cas register 6 76 176 276 376 xs7 w transmit cas register 7 77 177 277 377 xs8 w transmit cas register 8 78 178 278 378 xs9 w transmit cas register 9 79 179 279 379 xs10 w transmit cas register 10 7a 17a 27a 37a xs11 w transmit cas register 11 7b 17b 27b 37b xs12 w transmit cas register 12 7c 17c 27c 37c xs13 w transmit cas register 13 7d 17d 27d 37d xs14 w transmit cas register 14 7e 17e 27e 37e xs15 w transmit cas register 15 7f 17f 27f 37f xs16 w transmit cas register 16 80 180 280 380 pc1 r/w port configuration 1 81 181 281 381 pc2 r/w port configuration 2 82 182 282 382 pc3 r/w port configuration 3 83 183 283 383 pc4 r/w port configuration 4 84 184 284 384 pc5 r/w port configuration 5 85 gpc1 r/w global port configuration 1 table 11 control register address arrangement (contd) address register type comment
peb 22554 operational description e1 semiconductor group 101 09.98 after reset all control registers except the xfifo and xs1-16 are initialized to defined values. unused bits have to be set to logical 0. the status registers are only readable and are updated by the quadfalc. transmit fifo (write) xfifo up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a rme interrupt. writing data to xfifo can be done in 8-bit (byte) or 16-bit (word) access. the lsb is transmitted first. up to 32 bytes/16 words of transmit data can be written to the xfifo following a xpr (or alls) interrupt. command register (write) value after reset: 00 h rmc receive message complete confirmation from cpu to quadfalc that the current frame or data block has been fetched following a rpf or rme interrupt, thus the occupied space in the rfifo can be released. rres receiver reset the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one second timer and the receive signaling controller are reset. however the contents of the control registers will not be deleted. xrep transmission repeat if xrep is set to one together with xtf (write 24 h to cmdr), the quadfalc repeatedly transmits the contents of the xfifo (1 32 bytes) without hdlc framing fully transparently, i.e. without flag,crc. the cyclic transmission is stopped with a sres command or by resetting xrep. 7 0 xfifo xf7 xf0 (x00/x01) 70 cmdr rmc rres xrep xres xhf xtf xme sres (x02)
peb 22554 operational description e1 semiconductor group 102 09.98 note: during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. xres transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper will be reset. however the contents of the control registers will not be deleted. xhf transmit hdlc frame after having written up to 32 bytes to the xfifo, this command initiates the transmission of a hdlc frame. xtf transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. xme transmit message end indicates that the data block written last to the transmit fifo completes the current frame. the quadfalc can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres signaling transmitter reset the transmitter of the signaling controller will be reset. xfifo is cleared of any data and an abort sequence (seven 1's) followed by interframe time fill is transmitted. in response to xres a xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the quadfalc's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands.
peb 22554 operational description e1 semiconductor group 103 09.98 mode register (read/write) value after reset: 00 h mds2-0 mode select the operating mode of the hdlc controller is selected. 000 reserved 001 reserved 010 1 byte address comparison mode (ral1,2) 011 2 byte address comparison mode (rah1,2 and ral1,2) 100 no address comparison 101 1 byte address comparison mode (rah1,2) 110 reserved 111 no hdlc framing mode hrac hdlc receiver active switches the hdlc receiver to operational or inoperational state. 0 receiver inactive 1 receiver active div data inversion setting this bit will invert the internal generated hdlc data stream. 0 ? normal operation, hdlc data stream not inverted 1 ? hdlc data stream inverted 70 mode mds2 mds1 mds0 hrac div (x03)
peb 22554 operational description e1 semiconductor group 104 09.98 receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. rah1 ? value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. receive address byte high register 2 (read/write) value after reset: ff h rah2 value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h ral1 value of first individual low address byte receive address byte low register 2 (read/write) value after reset: ff h ral2... value of the second individually programmable low address byte. 710 rah1 0 (x04) 70 rah2 (x05) 70 ral1 (x06) 70 ral2 (x07)
peb 22554 operational description e1 semiconductor group 105 09.98 interrupt port configuration (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. ssyf select sync frequency only appilcable in master mode (lim0.mas = 1) and bit cmr2.dcf is cleared. 0 ? reference clock at port sync is 2.048 mhz 1 ? reference clock at port sync is 8 khz ic0, ic1 interrupt port configuration these bits define the function of the interrupt output stage (pin int): common configuration register 1 (read/write) value after reset: 00 h casm cas synchronization mode determines the synchronization mode of the channel associated signaling multiframe alignment. 0 synchronization is done in accordance to itu-t g. 732 1 synchronization is established when two consecutively correct multiframe alignment pattern are found. 70 ipc ssyf ic1 ic0 (08) ic1 ic0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high 70 ccr1 casm eits itf xmfa rft1 rft0 (x09)
peb 22554 operational description e1 semiconductor group 106 09.98 eits enable internal time-slot 0-31 signaling 0 internal signaling in time-slots 0-31 defined via registers rtr1- 4 or ttr1-4 is disabled. 1 internal signaling in time-slots 0-31 defined via registers rtr1- 4 or ttr1-4 is enabled. itf interframe time fill determines the idle (= no data to send) state of the transmit data coming from the signaling controller. 0 continuous logical 1 is output 1 continuous flag sequences are output (01111110 bit patterns) xmfa transmit multiframe aligned determines the synchronization between the framer and the corresponding signaling controller. 0 contents of the xfifo is transmitted without multiframe alignment. 1 contents of the xfifo is transmitted multiframe aligned. after receiving a complete multiframe in the time-slot mode (rtr1-4) an isr0.rme interrupt is generated, if no hdlc mode is enabled. in sa4-8 bit access xmfa is not valid. note: during the transmission of the xfifo content, the sypx or xmfs interval time should not be changed, otherwise the xfifo data has to be retransmitted. rft1, rft0rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after a rpf interrupt is given in the following table: the value of rft1, 0 can be changed dynamically. C if reception is not running or rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes
peb 22554 operational description e1 semiconductor group 107 09.98 C after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). note: it is seen that changing the value of rft1, 0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after a rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by a rmc command (see table below): common configuration register 2 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. radd receive address pushed to rfifo if this bit is set to 1, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.mds0) is pushed to rfifo. this function is applicable in non-auto mode. rcrc receive crc on/off only applicable in non-auto mode. if this bit is set to 1, the received crc checksum will be written to rfifo (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum will additionally be checked for correctness. if non-auto rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc4 . 0 rbc3 0 rbc1,0 rbc0 70 ccr2 radd rcrc xcrc (x0a)
peb 22554 operational description e1 semiconductor group 108 09.98 mode is selected, the limits for valid frame check are modified ( refer to rsis.vfr ). xcrc transmit crc on/off if this bit is set to 1, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo). the transmitted frame will be closed automatically with a closing flag. note: the quadfalc does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. receive timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 timeslot register these bits define the received time-slots on the system highway port rdo to be extracted to rfifo and marked. additionally these registers will control the rsigm marker which can be forced high during the respective time-slots independenltly of bit ccr1.eits. a one in the rtr1-4 bits will sample the corresponding time-slots and send their data to the rfifo of the signaling controller if bit ccr1.eits is set. assignments: ts0 ? time-slot 0 . . . ts31 ? time-slot 31 0 ? the corresponding time-slot is not extracted and stored into the rfifo. 70 rtr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (x0c) rtr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (x0d) rtr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (x0e) rtr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (x0f)
peb 22554 operational description e1 semiconductor group 109 09.98 1the contents of the selected time-slot will be stored in the rfifo. although the idle time-slots can be selected. this function will only become active if bits ccr1.eits is set. the corresponding time-slot will be forced high on marker pin rsigm. transmit timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 transmit timeslot register these bits define the transmit time-slots on the system highway to be inserted. additionally these registers will control the xsigm marker which can be forced high during the respective time-slots independently of bit ccr1.eits. a one in the ttr1-4 bits will insert the corresponding time-slot sourced by the xfifo in the data received on pin xdi, if bit ccr1.eits is set. if sic3.ttrf is set and ccr1.eits is cleared insertion of data received on port xsig is controlled by this registers. assignments: ts0 ? time-slot 0 . . . ts31 ? time-slot 31 0 ? the selected time-slot will not be inserted into the outgoing data stream. 1the contents of the selected time-slot will be inserted in the outgoing data stream from xfifo. this function will only become active if bits ccr1.eits is set. the corresponding time-slot will be forced high on marker pin xsigm. 70 ttr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (x10) ttr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (x11) ttr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (x12) ttr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (x13)
peb 22554 operational description e1 semiconductor group 110 09.98 interrupt mask register 0 ... 4 (read/write) value after reset: ff h , ff h , ff h , ff h , ff h imr0...imr4... interrupt mask register each interrupt source can generate an interrupt signal on port int (characteristics of the output stage are defined via register ipc). a 1 in a bit position of imr0 ... 4sets the mask active for the interrupt status in isr0 ... 4. masked interrupt statuses neither generate a signal on int, nor are they visible in registers gis or cis . moreover, they will C not be displayed in the interrupt status register if bit gcr.vis is set to 0 C be displayed in the interrupt status register if bit gcr.vis is set to 1. note: after reset, all interrupts are dis abled. 70 imr0 rme rfs t8ms rmb casc crc4 sa6sc rpf (x14) imr1 llbsc rdo alls xdu xmb xlsc xpr (x15) imr2 far lfa mfar t400ms ais los rar ra (x16) imr3 es sec lmfa16 ais16 ra16 rsn rsp (x17) imr4 xsp xsn (x18)
peb 22554 operational description e1 semiconductor group 111 09.98 framer mode register 0 (read/write) value after reset: 00 h xc1... xc0 transmit code serial code transmitter is independent to the receiver. 00... nrz (optical interface) 01... cmi (1t2b + hdb3), (optical interface) 10... ami (ternary or digital dual rail interface) 11... hdb3 code (ternary or digital dual rail interface) rc1... rc0 receive code serial code receiver is independent to the transmitter. 00... nrz (optical interface) 01... cmi (1t2b+hdb3), (optical interface) 10... ami (ternary or digital dual rail interface) 11... hdb3 code (ternary or digital dual rail interface) extd extended hdb3 error detection selects error detection mode. 0 only double violations are detected. 1 extended code violation detection: 0000 strings are detected additionally. thereafter, incrementation of code violation counter cvc is first done after receiving an additional four zeros. alm alarm mode selects the ais alarm detection mode. 0 ... the ais alarm will be detected according to ets300233. detection: an ais alarm will be detected if the incoming data stream contains less than 3 zeros within a period of 512 bits and a loss of frame alignment is indicated. recovery: the alarm will be cleared if 3 or more zeros within 512 bits will be detected or the fas word is found. 1 ... the ais alarm will be detected according to itu-t g.775 detection: an ais alarm will be detected if the incoming data stream contains for two consecutive doubleframe periods 70 fmr0 xc1 xc0 rc1 rc0 extd alm frs sim (x1c)
peb 22554 operational description e1 semiconductor group 112 09.98 (1024 bits) less than 3 zeros for each doubleframe period (512 bits). recovery: the alarm will be cleared if within two consecutive doubleframe periods 3 or more zeros for each period of 512 bits will be detected. frs force resynchronization a transition from low to high will initiate a resynchronization procedure of the pulse frame and the crc-multiframe (if enabled via bit fmr2.rfs1) starting directly after the old framing candidate. sim alarm simulation 0 normal operation. 1 initiates internal error simulation of ais, loss of signal, loss of synchronization, remote alarm, slip, framing errors, crc errors, and code violations. the error counters fec, cvc, cec1 will be incremented. framer mode register 1 (read/write) value after reset: 00 h mfcs multiframe force resynchronization only valid if crc multiframe format is selected (fmr2.rfs1/0=10). a transition from low to high will initiate the resynchronization procedure for crc-multiframe alignment without influencing doubleframe synchronous state. in case, automatic force resynchronization (fmr1.afr) is enabled and multiframe alignment can not be regained, a new search of doubleframe (and crc multiframe) is automatically initiated. afr automatic force resynchronization only valid if crc multiframe format is selected (fmr2.rfs1/0=10). if this bit is set, a search of doubleframe alignment is automatically initiated if two multiframe patterns with a distance of n 2ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained or command fmr1.mfcs has been issued. 70 fmr1 mfcs afr ensa pmod xfs ecm ssd0 xais (x1d)
peb 22554 operational description e1 semiconductor group 113 09.98 ensa enable s a -bit access via register xsa4-8 only applicable if fmr1.xfs is set to one. 0 normal operation. the s a -bit information will be taken from bits xsw.xy04 and written to bits rsw.ry04. 1 s a -bit register access. the s a -bit information will be taken from the registers xsa4-8. in addition, the received information will be written to registers rsa4-8. transmitting contents of registers xsa4-8 will be disabled if one of time-slot 0 transparent modes is enabled (xsp.tt0 or tswm.sa4-8). pmod pcm mode for e1 application this bit must be set low. switching from e1 to t1 or vv the device needs up to 10 m sec to settle up to the internal clocking. fmr1.pmod of all 4 channels has to be set equally. 0 pcm 30 or e1 mode. 1 pcm 24 or t1 mode. xfs transmit framing select selection of the transmit framing format could be done independent of the receive framing format. 0 doubleframe format enabled. 1 crc4-multiframe format enabled. ecm error counter mode the function of the error counters will be determined by this bit. 0 ? before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters will be reset with the rising edge of the corresponding bits in the dec register. 1 every second the error counter will be latched and then automatically be reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided. ssd0 select system data rate 0 fmr1.ssd0 and sic1.sd1 define the data rate on the system highway. programming is done with ssd1/ssd0 in the following table. 002.048 mbit/s
peb 22554 operational description e1 semiconductor group 114 09.98 014.096 mbit/s 108.192 mbit/s 1116.384 mbit/s xais transmit ais towards remote end sends ais via ports xl1, xl2, xoid towards the remote end. the outgoing data stream which could be looped back via the local loop to the system interface will not be affected. framer mode register 2 (read/write) value after reset: 00 h rfs1... rfs0... receive framing select 00 ... doubleframe format 01 ... doubleframe format 10 ... crc4 multiframe format 11 ... crc4 multiframe format with modified crc4 multiframe alignment algorithm (interworking according to itu-t g.706 annex b). setting of fmr3.extiw changes the reaction after the 400 msec timeout. rtm receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a free running mode without any possibility to actualize the time slot assignment to a new frame position in case of re-synchronization of the receiver. this function can be used in conjunction with the disable ais to system interface feature (fmr2.dais) to realize undisturbed transparent reception. this bit should be enabled in case of unframed data reception mode. dais disable ais to system interface 0 ais is automatically inserted into the data stream to rdo if quadfalc is in asynchronous state. 1 automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. 70 fmr2 rfs1 rfs0 rtm dais sais plb axra almf (x1e)
peb 22554 operational description e1 semiconductor group 115 09.98 sais send ais towards system interface sends ais via output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb payload loopback 0 normal operation. payload loop is disabled. 1... the payload loopback will loop the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received at port xdi, xsig, sypx and xmfs will be ignored. with xsp.tt0=1 timeslot 0 will also be looped. if xsp.tt0=0 timeslot 0 will be generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. during payload loop is active a write access to register xc1 will set the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation. axra automatic transmit remote alarm 0 ... normal operation 1 ... the remote alarm bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be reset. additionally in multiframe format fmr2.rfs1=1 and fmr3.extiw =1 and the 400 msec timeout has elapsed, the remote alarm bit will be active in the outgoing data stream. in multiframe synchronous state the outgoing remote alarm bit is cleared. almf automatic loss of multiframe 0 ... normal operation 1 ... the receiver will search a new basic- and multiframing if more than 914 crc errors have been detected in a time interval of one second. the internal 914 crc error counter will be reset if the multiframe synchronization is found. incrementing the counter is only enabled in the multiframe synchronous state.
peb 22554 operational description e1 semiconductor group 116 09.98 channel loop back (read/write) value after reset: 00 h eclb enable channel loop back 0 ... disables the channel loop back. 1 ... enables the channel loop back selected by this register. cla4cla0 channel address for loop back cla = 031 selects the channel. during looped back the contents of the assigned outgoing channel on ports xl1/xdop/xoid and xl2/xdon is equal to the idle channel code programmed at register idle. transmit service word pulseframe (read/write) value after reset: 00 h xsis spare bit for international use first bit of the service word. only significant in doubleframe format. if not used, this bit should be fixed to 1. if one of the time-slot 0 transparent modes is enabled (bit xsp.tt0, or tswm.tsis), bit xsw.xsis will be ignored. xtm transmit transparent mode 0ports sypx / xmfs define the frame / multiframe begin on the transmit system highway. the transmitter is usually synchronized on this externally sourced frame boundary and generates the fas bits according to this framing. any change of the transmit time-slot assignment will subsequently produce a change of the fas bit positions. 1 disconnects the control of the transmit system interface from the transmitter. the transmitter is now in a free running mode without any possibility to actualize the multiframe position. the framing (fas bits) generated by the transmitter will not be ?disturbed (in case of 70 loop eclb cla4 cla0 (x1f) 70 xsw xsis xtm xra xy0 xy1 xy2 xy3 xy4 (x20)
peb 22554 operational description e1 semiconductor group 117 09.98 changing the transmit time-slot assignment) by the transmit system highway unless register xc1 is written. useful in loop-timed applications. for proper operation the transmit elastic buffer (2 frames, sic1.xbs1/0= 10) has to be enabled. xra transmit remote alarm 0 normal operation. 1 sends remote alarm towards remote end by setting bit 3 of the service word. if time-slot 0 transparent mode is enabled via bit xsp.tt0 or tswm.tra bit is set, bit xsw.xra will be ignored. xy0xy4 spare bits for national use (y-bits, s n -bits, s a -bits) these bits are inserted in the service word of every other pulseframe if s a -bit register access is disabled (fmr1.ensa = 0). if not used, they should be fixed to 1. if one of the time-slot 0 transparent modes is enabled (bit xsp.tt0 or tswm.tsa4-8), bits xsw.xy04 will be ignored. transmit spare bits (read/write) value after reset: 00 h casen channel associated signaling enable 0 normal operation. 1 a one in this bit position will cause the transmitter to send the cas information stored in the xs1-16 registers in the corresponding time slots. tt0 time-slot 0 transparent mode 0 normal operation. 1 all information for time-slot 0 at port xdi will be inserted in the outgoing pulseframe. all internal information of the quadfalc (framing, crc, s a /s i bit signaling, remote alarm) will be ignored. this function is mainly useful for system test applications (test loops). priority sequence of transparent modes: xsp.tto > tswm. 70 xsp casen tt0 ebp axs xsif xs13 xs15 (x21)
peb 22554 operational description e1 semiconductor group 118 09.98 ebp e- bit polarity 0 in the basic - or multiframe asynchronous state the e-bit will be set to zero. 1 in the basic - or multiframe asynchronous state the e-bit will be set to one. if automatic transmission of sub-multiframe status is enabled by setting bit xsp.axs and the receiver has been lost multiframe synchronization, the e bit with the programmed polarity will be inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time-slot 0 transparent mode and transparent si bit in service word are both disabled). axs automatic transmission of submultiframe status only applicable to crc multiframe. 0 normal operation. 1 information of submultiframe status bits rsp.si1 and rsp.si2 will be automatically inserted in s i -bit positions of the outgoing crc multiframe (rsp.si1 ? s i -bit of frame 13; rsp.si2 ? s i -bit of frame 15). contents of xsp.xs13 and xsp.xs15 will be ignored. if one of the time-slot 0 transparent modes xsp.tt0 or tswm.tsis is enabled, bit xsp.axs has no function. xsif transmit spare bit for international use (fas word) first bit in the fas word. only significant in doubleframe format. if not used, this bit should be fixed to 1. if one of the time-slot 0 transparent modes is enabled (bits xsp.tt0, or tswm.tsif), bit xsp.xsif will be ignored. xs13 transmit spare bit (frame 13, crc-multiframe) first bit in the service word of frame 13 for international use. only significant in crc-multiframe format. if not used, this bit should be fixed to 1. the information of xsp.xs13 will be shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled via bit xsp.axs, or, if one of the time-slot 0 transparent modes xsp.tt0 or tswm.tsis is enabled, bit xsp.xs13 will be ignored.
peb 22554 operational description e1 semiconductor group 119 09.98 xs15 transmit spare bit (frame 15, crc-multiframe) first bit in the service word of frame 15 for international use. only significant in crc-multiframe format. if not used, this bit should be fixed to 1. the information of xsp.xs15 will be shifted into internal transmission buffer with beginning of the next following transmitted crc multiframe. if automatic transmission of submultiframe status is enabled via bit xsp.axs, or, if one of the time-slot 0 transparent modes xsp.tt0 or tswm.tsif is enabled, bit xsp.xs15 will be ignored. transmit control 0 (read/write) value after reset: 00 h sa8esa4e sa bit signaling enable 0 standard operation. 1 setting this bit it will be possible to send / receive a lapd protocol in any combination of the sa8- sa4 bit positions in the outgoing / incoming data stream. the on chip signaling controller has to be configured in the hdlc/lapd mode. in transmit direction together with these bits the tswm.tsa8-4 bits must be set to enable transmission to the remote end transparently through the falc. xco10xco8 transmit offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse at port sypx / xmfs is active refer to register xc1. 70 xc0 sa8e sa7e sa6e sa5e sa4e xco10 xco9 xco8 (x22)
peb 22554 operational description e1 semiconductor group 120 09.98 transmit control 1 (read/write) value after reset: 9c h a write access to this address resets the transmit elastic buffer to its basic starting position. therefore, updating the value should only be done when the quadfalc is initialized or when the buffer should be centered. as a consequence a transmit slip may occur. xco7xco0 transmit offset calculation of delay time t (sclkx cycles) depends on the value x of the ?transmit offset register xc1/0: 0 t 3 + sc/sd : x = 3 + sc/sd - t 4+ sc/sd t max. delay :x = 2051 - t + sc/sd delay time t = time between beginning of time-slot 0 ( bit 0 , channel phase 0) at xdi / xsig and the initial edge of sclkx after sypx / xmfs goes active. see figure 20 + 21. with max. delay = (256 * sc/sd) -1 with sc = system clock defined by sic1.ssc1/0 with sd = system data rate receive control 0 (read/write) value after reset: 00 h swd service word condition disable 0 standard operation. three or four consecutive incorrect service words (depending on bit rc1.asy4) will cause loss of synchronization. 1 errors in service words have no influence when in synchronous state. however, they are used for the resynchronization procedure. 70 xc1 xco7 xco0 (x23) 70 rc0 swd asy4 crci xcrci rdis rco10 rco9 rco8 (x24)
peb 22554 operational description e1 semiconductor group 121 09.98 asy4 select loss of sync condition 0 standard operation. three consecutive incorrect fas words or three consecutive incorrect service words will cause loss of synchronization. 1 four consecutive incorrect fas words or four consecutive incorrect service words will cause loss of synchronization. the service word condition may be disabled via bit rc1.swd. crci automatic crc4 bit inversion if set, all crc bits of one outgoing submultiframe are inverted in case a crc error is flagged for the previous received submultiframe. this function is logically ored with rc0.xcrci. xcrci transmit crc4 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis receive data input sense 0 inputs: rdip, rdin active low, input roid is active high 1 inputs: rdip, rdin active high, input roid is active low rco10rco8receive offset / receive frame marker offset depending on the rp(a-d) pin function different offsets could be programmed. the sypr and the rfm pin function could not be selected in parallel. receive offset (pc(1-4).rpc(2-0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure ) . calculation of delay time t (sclkr cycles) depends on the value x of the ?receive offset register rc1/0. for programing refer to register rc1. receive frame marker offset (pc(1-4).rpc(2-0) = 001) offset programming of the receive frame marker which is output on port sypr . the receive frame marker could be activated during any bit position of the current frame. calculation of the value x of the ?receive offset register rc1/0 depends on the bit position bp which should be marked and sclkr. refer to register rc1.
peb 22554 operational description e1 semiconductor group 122 09.98 receive control 1 (read/write) value after reset: 9c h rco7rco0 receive offset / receive frame marker offset depending on the rp(a-d) pin function different offsets could be programmed. the sypr and the rfm pin function could not be selected in parallel. receive offset (pc(1-4).rpc(2-0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 17 ) . calculation of delay time t (sclkr cycles) depends on the value x of the ?receive offset register rc1/0: 0 t 4 : x= 4- t 5 t max. delay : x= 2052 - t with max. delay = (256*sc/sd) -1 with sc = system clock defined by sic1.ssc1/0 with sd = 2.048 mhz delay time t = time between beginning of time-slot 0 at rdo and the initial edge of sclkr after sypr goes active. receive frame marker offset (pc(1-4).rpc(2-0) = 001) offset programming of the receive frame marker which is output on multifunction port rfm. the receive frame marker could be activated during any bit position of the entire frame and depends on the selected system clock rate. calculation of the value x of the ?receive offset register rc1/0 depends on the bit position bp which should be marked : 0 bp 2045 : x = bp + 2 2046 bp 2047 : x= bp - 2046 ) e.g: 2.048 mbit/s: bp = 0-255; .... 16.384 mbit/s: bp = 0-2047 70 rc1 rco7 rco0 (x25)
peb 22554 operational description e1 semiconductor group 123 09.98 transmit pulse-mask 0...2 (read/write) value after reset: 7b h , 03 h , 00 h the transmit pulse shape which is defined in itu-t g.703 will be output on pins xl1 and xl2. the level of the pulse shape can be programmed via registers xpm2-0 to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape will be internally devided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value will define the level of the analog voltage on pins xl1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape. the four 5 bit values will be sent in the following sequence: xp04-00: first pulse shape level xp14-10: second pulse shape level xp24-20: third pulse shape level xp34-30: fourth pulse shape level changing the lsb of each subpulse in registers xpm2-0 will change the amplitude of the differential voltage on xl1/2 by approximately 80 mv. example: 120 w interface and wired as shown in figure 22 . xpm04-00: 1b h or 27 decimal xpm14-10: 1b h or 27 decimal xpm24-20: 00 h xpm34-30: 00 h programming values for xpm0-2: 7b h , 03 h , 00 h xlt transmit line tri-state 0 normal operation 1 transmit line xl1/xl2 or xdop/xdon are switched into high impedance state. if this bit is set the transmit line monitor status information will be frozen. daxlt... disable automatic tristating of xl1/2 0... normal operation. if a short is detected on pins xl1/2 the transmit line monitor will set the xl1/2 outputs into a high impedance state. 70 x p m 0 x p 1 2 x p 1 1 xp10 xp04 xp03 xp02 xp01 xp00 (x26) xpm1 xp30 xp24 xp23 xp22 xp21 xp20 xp14 xp13 (x27) xpm2 xllp xlt daxlt xp34 xp33 xp32 xp31 (x28)
peb 22554 operational description e1 semiconductor group 124 09.98 1... if a short is detected on xl1/2 pins automatic setting these pins into a high impedance (by the xl-monitor) state will be disabled. xllp reserved 0 normal operation 1 reserved ( not to be used) transparent service word mask (read/write) value after reset: 00 h tswm7tswm0transparent service word mask tsis transparent si bit in service word 0 the si bit will be generated internally. 1 the si bit in the service word will be taken from port xdi and transparently passed through the quadfalc without any changes. the internal information of the quadfalc (register xsw) will be ignored. tsif transparent si bit in fas word 0 the si bit will be generated internally. 1 the si bit in the fas word will be taken from port xdi and routed transparently through the quadfalc without any changes. the internal information of the quadfalc (register xsw) will be ignored. tra transparent remote alarm 0 the remote alarm bit will be generated internally. 1 the a bit will be taken from port xdi and routed transparently through the quadfalc without any changes. the internal information of the quadfalc (register xsw) will be ignored. tsa4tsa8... transparent sa4...8 bit 0 the sa4-8 bit will be generated internally. 1 the sa4-8 bit will be taken from port xdi or from the internal signaling controller if enabled and transparently passed 70 tswm tsis tsif tra tsa4 tsa5 tsa6 tsa7 tsa8 (x29)
peb 22554 operational description e1 semiconductor group 125 09.98 through the quadfalc without any changes. the internal information of the quadfalc (registers xsw and xsa4-8) will be ignored. idle channel code register (read/write) value after reset: 00 h idl7idl0 idle channel code if channel loop back is enabled by programming loop.eclb=1, the contents of the assigned outgoing channel on ports xl1/xl2 resp. xdop/xdon is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels selected via the idle channel registers icb1icb4. idl7 will be transmitted first. transmit sa4-8 register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h , 00 h xsa8xsa4 transmit s a -bit data the sa-bit register access is enabled by setting bit fmr1.ensa = 1. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of these registers xsa4-8 will be copied into a shadow register. the contents will subsequently sent out in the service words of the next outgoing crc multiframe (or doubleframes) if none of the time-slot 0 transparent modes is enabled. xs40 will be sent out in bit position 4 in frame 1, xs47 in frame 15. the transmit 70 idle idl7 idl0 (x2b) 70 xsa4 xs47 xs46 xs45 xs44 xs43 xs42 xs41 xs40 (x2c) xsa5 xs57 xs56 xs55 xs54 xs53 xs52 xs51 xs50 (x2d) xsa6 xs67 xs66 xs65 xs64 xs63 xs62 xs61 xs60 (x2e) xsa7 xs77 xs76 xs75 xs74 xs73 xs72 xs71 xs70 (x2f) xsa8 xs87 xs86 xs85 xs84 xs83 xs82 xs81 xs80 (x30)
peb 22554 operational description e1 semiconductor group 126 09.98 multiframe begin interrupt xmb request that these registers should be serviced. if requests for new information are ignored, current contents will be repeated. framer mode register 3 (read/write) value after reset: 00 h xld transmit llb down code 0 normal operation. 1 a one in this bit position will cause the transmitter to replace normal transmit data with the llb down (deactuate) code continuously until this bit is reset. the llb down code will be optionally overwritten by the timeslot 0 depending on bit lcr1.llbf. xlu transmit llb up code 0 normal operation. 1 a one in this bit position will cause the transmitter to replace normal transmit data with the llb up code continuously until this bit is reset. the llb up code will be overwritten by the timeslot 0 depending on bit lcr1.llbf. for proper operation bit fmr3.xld must be cleared. cmi select cmi precoding only valid if cmi code (fmr0.xc1/0=01) is selected. this bit defines the cmi precoding and influences only the transmit data and not the receive data. 0 cmi with hdb3 precoding 1 cmi without hdb3 precoding sa6sy receive sa6 access synchron mode only valid if multiframe format (fmr2.rfs1/0=1x) is selected. 0 the detection of the predefined sa6 bit pattern (refer to chapter sa6 bit detection according to ets 300233) is done independently of the multiframe synchronous state. 70 fmr3 xld xlu cmi sa6sy extiw (x31)
peb 22554 operational description e1 semiconductor group 127 09.98 1 the detection of the sa6 bit pattern is done synchronously to the multiframe. extiw extended crc4 to non crc4 interworking only valid in multiframe format. this bit selects the reaction of the synchronizer after the 400 msec timeout has been elapsed and starts transmitting a remote alarm if fmr2.axra is set. 0 the crc4 to non crc4 interworking is done as described in itu-t g. 706 annex b. 1 the interworking is done according to itu-t g. 706 with the exception that the synchronizer will still search the multiframing even if the 400 msec timer is expired. switching into doubleframe format is disabled. if fmr2.axra is set the remote alarm bit will be active in the outgoing data stream until the multiframe is found. idle channel register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ic0ic31 idle channel selection bits these bits define the channels (time-slots) of the outgoing pcm frame to be altered. assignments: ic0 ? time-slot 0 ic1 ? time-slot 1 ic31 ? time-slot 31 0 normal operation. 1 idle channel mode. the contents of the selected time-slot is overwritten by the idle channel code defined via register idle. 70 icb1 ic0 ic1 ic2 ic3 ic4 ic5 ic6 ic7 (x32) icb2 ic8 ic9 ic10 ic11 ic12 ic13 ic14 ic15 (x33) icb3 ic16 ic17 ic18 ic19 ic20 ic21 ic22 ic23 (x34) icb4 ic24 ic25 ic26 ic27 ic28 ic29 ic30 ic31 (x35)
peb 22554 operational description e1 semiconductor group 128 09.98 note: although time-slot 0 can be selected via bit ic0, its contents is only altered if the transparent mode is selected (xsp.tt0). line interface mode 0 (read/write) value after reset: 00 h xfb transmit full bauded mode only applicable for dual rail mode (bit lim1.drs = 1). 0output signals xdop/xdon are half bauded (normal operation). 1output signals xdop/xdon are full bauded. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. xdos transmit data out sense 0 output signals xdop/xdon are active low. output xoid is active high (normal operation). 1 output signals xdop/xdon are active high. output xoid is active low. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. the transmit frame marker xfm is independent of this bit. eqon receive equalizer on 0 -10 db receiver: short haul mode 1 -34 db receiver, long haul mode ll local loop 0 normal operation 1 local loop active. the local loopback mode disconnects the receive lines rl1/rl2 resp. rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream will be undisturbed transmitted on the line. receiver and transmitter coding must be identical. operates in analog and digital line 70 lim0 xfb xdos eqon ll mas (x36)
peb 22554 operational description e1 semiconductor group 129 09.98 interface mode. in analog line interface mode data is transfered through the complete analog receiver. mas master mode 0 slave mode 1 ? master mode on. setting this bit the dco-r circuitry is frequency synchronized to the clock (2.048 mhz) supplied by sync. if this pin is connected to vss or vdd the dco-r circuitry is centered and no receive jitter attenuation is performed. the generated clocks are stable. line interface mode 1 (read/write) value after reset: 00 h ril2ril0 receive input threshold only valid if analog line interface is selected (lim1.drs=0. no signal will be declared if the voltage between pins rl1 and rl2 drops below the limits programmed via bits ril2-0 and the received data stream has no transition for a period defined in the pcd register. the threshold where no signal will be declared is programmable via the ril2-0 bits depending of bit lim0.eqon. lim0.eqon = 0 (short haul mode): 000 = 0.9 v 001 = 0.7 v 010 = 0.6 v 011 = 0.4 v 100 = 0.3 v 101 = 0.2 v 110 = 0.07 v 111 = 0.05 v lim0.eqon = 1 (long haul mode): 000 = 1.7 v 001 = 0.8 v 010 = 0.8 v 011 = 0.5 v 100 = 0.5 v 101 = 0.2 v 70 lim1 ril2 ril1 ril0 jatt rl drs (x37)
peb 22554 operational description e1 semiconductor group 130 09.98 110 = 0.1 v 111 = not assigned jattrl... transmit jitter attenuator / remote loop 00 ... normal operation. the transmit jitter attenuator is disabled. transmit data will bypass the buffer. 01 ... remote loop active without transmit jitter attenuator enabled. transmit data will bypass the buffer. 10 ... not defined 11 ... remote loop and jitter attenuator active. received data from pins rl1/2 or rdip/n or roid will be sent jitter free on ports xl1/2 or xdop/n or xoid. the dejittered clock is generated by the dco-x circuitry. drs dual rail select 0 ... the ternary interface is selected. multifunction ports rl1/2 and xl1/2 become analog in/outputs. 1 ... the digital dual rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins xdop/xdon.
peb 22554 operational description e1 semiconductor group 131 09.98 pulse count detection register (read/write) value after reset: 00 h pcd7pcd0 pulse count detection a los alarm will be detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable via the pcd register and can be calculated as follows: t= 16(n+1) ; with 0 =< n =< 255. the maximum time is: 256 x 16 x 488 ns = 2 ms. every detected pulse will reset the internal pulse counter. the counter will be clocked with the receive clock rclk. pulse count recovery (read/write) value after reset: 00 h pcr7pcr0 pulse count recovery a los alarm will be cleared if a pulse density is detected in the received bit stream. the number of pulses m which must occur in the predefined pcd time interval is programmable via the pcr register and can be calculated as follows: m = n+1 ; with 0 =< n =< 255. the time interval starts with the first detected pulse transition. with every received pulse a counter will be incremented and the actual counter is compared with the contents of pcr register. if the pulse number >= the pcr value the los alarm will be reset otherwise the alarm will still be active. in this case the next detected pulse transition will start a new time interval. 70 pcd pcd7 pcd0 (x38) 70 pcr pcr7 pcr0 (x39)
peb 22554 operational description e1 semiconductor group 132 09.98 line interface mode 2 (read/write) value after reset: 00 h lbo1 line build-out in long haul applications lim0.eqon = 1 a transmit filter can be optionally placed on the transmit path to attenuate the data on pins xl1/2. to meet the line build-out defined by ftz221 registers xpm2-0 should be programmed as follows: 0 0 db 1 ftz221 template --> xpm2-0 = tbd. scf select corner frequency of dco-r setting this bit will reduce the corner frequency of the dco-r circuit by the factor of ten to 0.2 hz. note: reducing the corner frequency of the dco-r circuitry will increase the synchronization time before the frequencies are synchronized. elt enable loop-timed 0 normal operation 1 transmit clock is generated from the clock supplied by mclk which is synchronized to the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. refer to register xsw.xtm. for correct operation of loop timed the remote loop (bit lim1.rl = 0) must be inactive and bit cmr1.dxss must be cleared. loop code register 1 (read/write) value after reset: 00 h eprm enable pseudo random bit sequence monitor 0 pseudo random bit sequence (prbs) monitor is disabled. 70 lim2 lbo1 scf elt (x3a) 70 lcr1 eprm xprbs ldc1 ldc0 lac1 lac0 fllb llbp (x3b)
peb 22554 operational description e1 semiconductor group 133 09.98 1 prbs is enabled. setting this bit enables incrementing the cec2 error counter with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr1.llbsc is generated. the current status of the prbs synchronizer is indicated by bit rsp.llbad. xprbs transmit pseudo random bit sequence a one in this bit position enables transmitting of a pseudo random bit sequence to the remote end. depending on pit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 ( itu-t o. 151). ldc10... length deactuate (down) code these bits defines the length of the llb deactuate code which is programmable in register lcr2. 00 length: 5 bit 01 length: 6 bit, 2 bit, 3 bit 10 length: 7 bit 11 length: 8 bit, 2 bit, 4bit lac10... length actuate (up) code these bits defines the length of the llb actuate code which is programmable in register lcr3. 00 length: 5 bit 01 length: 6 bit, 2 bit, 3 bit 10 length: 7 bit 11 length: 8 bit, 2 bit, 4 bit fllb framed line loopback / invert prbs depending on bit lcr1.xprbs this bit enables different functions: lcr1.xprbs=0: 0 the line loopback code is transmitted including framing bits. 1 the line loopback code is transmitted unframed.
peb 22554 operational description e1 semiconductor group 134 09.98 invert prbs lcr1.xprbs=1: 0 the generated prbs is transmitted not inverted. 1 the prbs is transmitted inverted. llbp line loopback pattern lcr1.xprbs=0 0 fixed line loopback code : 001 or 00001. 1 enable user programmable line loopback code via register lcr2/3. lcr1.xprbs=1 or lcr1.eprm = 1 0 2 15 -1 1 2 20 -1 loop code register 2 (read/write) value after reset: 00 h ldc7ldc0 line loopback deactuate code if enabled by bit fmr3.xld the llb deactuate code will automatically repeat until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmittted last. for correct operations bit lcr1.xprbs has to cleared. loop code register 3 (read/write) value after reset: 00 h lac7lac0 line loopback actuate code if enabled by bit fmr3.xlu the llb actuate code will automatically repeat until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmittted last. for correct operations bit lcr1.xprbs has to cleared. 70 lcr2 ldc7 ldc0 (x3c) 70 lcr3 lac7 lac0 (x3d)
peb 22554 operational description e1 semiconductor group 135 09.98 system interface control 1 (read/write) value after reset: 00 h ssc1...0 select system clock sic1.ssc1/0 define the clocking rate on the system highway. 002.048 mhz 014.096 mhz 108.192 mhz 1116.384 mhz ssd1 select system data rate 1 sic1.ssd1 and fmr1.ssd0 define the data rate on the system highway. programming ssd1/ssd0 and corresponding data rate is shown below. 002.048 mbit/s 014.096 mbit/s 108.192 mbit/s 1116.384 mbit/s rbs1...0 receive buffer size 00 buffer size : 2 frames 01 buffer size : 1 frame 10 buffer size : 96 bits 11 by-pass of receive elastic store bim bit interleaved mode 0byte interleaved mode 1bit interleaved mode xbs1...0 transmit buffer size 00 by-pass of transmit elastic store 01 buffer size : 1 frame 10 buffer size : 2 frames 11 buffer size : 96 bits 70 sic1 ssc1 ssd1 rbs1 rbs0 ssc0 bim xbs1 xbs0 (x3e)
peb 22554 operational description e1 semiconductor group 136 09.98 system interface control 2 (read/write) value after reset: 00 h ffs force freeze signaling setting this bit disables updating of the receive signaling buffer and current signaling information is frozen. after resetting this bit and receiving a complete superframe updating of the signaling buffer is started again. the freeze signaling status could be also automatically generated by detecting the loss of signal alarm or a loss of cas frame alignment or a receive slip (only if external register access via rsig is enabled). this automatic freeze signaling function is logically ored with this bit. the current internal freeze signaling status is output on pin rp(a-d) / pin function freez which is selected by pc(1-4).rpc(2-0) = 110. additionally this status is also available in register sis.sfs. ssf serial signaling format only applicable if pin function r/xsig is selected. 0 bits 1-4 in all time-slots except time-slots 0 +16 are cleared. 1 bits 1-4 in all time-slots except time-slots 0 +16 are set high. crb center receive elastic buffer only applicable if the time-slot assigner is disabled ( pc1-4.rpc2-0 = 001 ) , no external or internal synchronous pulse receive is generated. a transition from low to high will force a receive slip and the read- pointer of the receive elastic buffer is centered. the delay through the buffer is set to one half of the current buffer size. it should be hold high for at least two 2.048 mhz periods before it is cleared. sics2 0 system interface channel select only applicable if the system clock rate is greater than 2.048 mhz . received data is transmitted on pin rdo / rsig or received on xdi / xsig with the selected system data rate. if the data rate is greater than 2.048 mbit/s the data is output or sampled in half , a quarter or a 1/8 of the 125 sec. they will not be repeated. the time where the data is active during a 488 nsec time-slot is called in the following a channel phase. rdo / rsig are cleared while xdi / xsig are 70 sic2 ffs ssf crb sics2 sics1 sics0 (x3f)
peb 22554 operational description e1 semiconductor group 137 09.98 ignored for the remaining time of the 488 nsec or for the remaining channel phases. the channel phases are selectable with these bits. 000 data active in channel phase 1, valid if system data rate is 16/8/4mbit/s 001 data active in channel phase 2, valid if system data rate is 16/8/4mbit/s 010 data active in channel phase 3, valid if data rate is 16 / 8 mbit/s 011 data active in channel phase 4, valid if data rate is 16 / 8 mbit/s 100 data active in channel phase 5 , valid if data rate is 16 mbit/s 101 data active in channel phase 6 , valid if data rate is 16 mbit/s 110 data active in channel phase 7, valid if data rate is 16 mbit/s 111 data active in channel phase 8 , valid if data rate is 16 mbit/s system interface control 3 (read/write) value after reset: 00 h casmf cas multiframe begin marker 0the time-slot 0 multiframe begin is asserted on pin rp(a-d) / pin function rmfb. 1the time-slot 16 cas multiframe begin is asserted on pin rp(a- d) / pin function rmfb. resx rising edge synchronous pulse transmit depending on this bit all transmit system interface data and marker are clocked off or sampled with the selected active edge. 0 sypx is latched with the first falling (active) edge of the sclkx clock. 1 sypx is latched with the first rising (active) edge of the sclkx clock. the sypx pin function is selected by pc(1-4).xc(2-0) = 0000. resr rising edge synchronous pulse receive depending on this bit all receive system interface data and marker are clocked off with the selected active edge. 70 sic3 casmf resx resr ttrf daf (x40)
peb 22554 operational description e1 semiconductor group 138 09.98 0 sypr is latched with the first falling edge of the sclkr clock. 1 sypr is latched with the first rising edge of the sclkr clock. the sypr pin function is selected by pc(1-4).rpc(2-0) = 000. ttrf ttr register function setting this bit the function of the ttr1-4 registers are changed. a one in each ttr register will force the xsigm marker high for the respective time-slot and controls sampling of the time-slots provided on pin xsig. xsig is selected by pc(1-4).xpc(2-0). daf disable automatic freeze 0 signaling is automaticly frozen if one of the following alarms occured: loss of signal (frs0.los), loss of cas frame alignment (frs1.ts16lfa) , or receive slips (isr3.rsp/n). 1 automatic freezing of signaling data is disabled. updating of the signaling buffer is also done if one of the above described alarm conditions is active. however, updating of the signaling buffer is stopped if sic2.ffs is set. significant only if the serial signaling access is enabled. clock mode register 1 (read/write) value after reset: 00 h drss1 ... 0 dco-r synchronization clock source these bits select the reference clock source for the dco-r circuitry. 00 receive reference clock generated by the dpll of channel 1 01 receive reference clock generated by the dpll of channel 2 10 receive reference clock generated by the dpll of channel 3 11 receive reference clock generated by the dpll of channel 4 note: after reset all dco-r circuitries will synchronize on the clock sourced by the dpll of channel 1 . each channel have to be configured individually. if lim0.mas is set the dco-r circuitry will synchronize on the clock applied to port sync. 70 cmr1 drss1 drss0 rs1 rs0 dcs stf dxja dxss (x44)
peb 22554 operational description e1 semiconductor group 139 09.98 rs1 ... 0 select rclk source these bits select the source of rclk. 00 extracted receive clock, generated by the dpll 01 extracted receive clock with the option in case of an active los alarm this pin is set high. 10 dejittered 2.048 mhz clock generated by the internal dco-r circuitry. 11 dejittered 8.192 mhz clock generated by the internal dco-r circuitry. dcs disable clock switching in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of loss of signal los the dco-r switches automatically to the clock sourced by port sync. setting this bit automatic switching from rclk to sync is disabled. stf select tclk frequency only applicable if the pin function tclk port xp(a-d) is selected by pc(1-4).xpc(2-0) = 011. data on xl1/2 (xdop/n / xoid) are clocked off with tclk. 0 2.048 mhz 1 8.192 mhz dxja disable internal transmit jitter attenuation setting this bit disables the transmit jitter attenuation. reading the data out of the transmit elastic buffer and transmitting on xl1/2 (xdop/n / xoid) is done with the clock provided on pin tclk. in transmit elastic buffer bypass mode the transmit clock is taken from sclkx, independent of this bit. dxss dco-x synchronization clock source 0 the dco-x circuitry of each channel will synchronize to the internal reference clock which is sourced by sclkx/r or rclk. since there are many reference clock opportunities the following internal priorization in descenting order from left to right is realized: lim1.rl > cmr2.dxss > lim2.elt > current working clock of transmit system interface. if one of these bits is set the corresponding reference clock is taken.
peb 22554 operational description e1 semiconductor group 140 09.98 1 dco-x synchronizes to an external reference clock provided by pin xp(a-d) pin function tclk, if no remote loop is active. tclk is selected by pc(1-4).xpc(2-0) = 011. clock mode register 2 (read/write) value after reset: 00 h dcf dco-r center- frequency disabled 0 the dco-r circuitry may be frequency centered - in master mode if no reference clock on pin sync is provided or - in slave mode if a loss of signal occurs in combination with no clock on pin sync or - a gapped clock is provided at pin rclki and this clock is inactive or stopped. 1 the center function of the dco-r circuitry is disabled. the generated clock (dco-r) is frequency frozen in that moment when no clock is available at pin sync or pin rclki. the dco-r circuitry will starts synchronization as soon as a clock at pins sync or rclki appears. irsp internal receive system frame sync pulse 0 the frame sync pulse for the receive system interface is sourced by sypr . 1 the frame sync pulse for the receive system interface is internally sourced by the dco-r circuitry of each channel. this internally generated frame sync could be output active low on pin rp(a-d). rpc(2-0) = 001. programming the receive time- slot offset is also done in the same way as it is done for the external sypr . for correct operation bit irsc must be set. sypr is ignored. irsc internal receive system clock only applicable if bit gpc1.smm is cleared. if gpc1.smm is set sclkr1 of channel 1 provides the working clock for all four channels. 70 cmr2 dcf irsp irsc ixsp ixsc (x45)
peb 22554 operational description e1 semiconductor group 141 09.98 0 the working clock for the receive system interface is sourced by sclkr of each channel or in receive elastic buffer bypass mode from the corresponding extracted receive clock rclk. 1 the working clock for the receive system interface is sourced internally by dco-r or in bypass mode by the extracted receive clock of each channel. sclkr is ignored. ixsp internal transmit system frame sync pulse 0 the frame sync pulse for the transmit system interface is sourced by sypx . 1 the frame sync pulse for the transmit system interface is internally sourced by the dco-r circuitry of each channel. additionally, the external xmfs signal defines the transmit multiframe begin. xmfs is enabled or disabled via the multifunction ports. for correct operation bits cmr2.ixsc / irsc must be set. sypx is ignored. ixsc internal transmit system clock only applicable if bit gpc1.smm is cleared. if gpc1.smm is set sclkx1 of channel 1 provides the working clock for all four channels. 0 the working clock for the transmit system interface is sourced by sclkx of each channel. 1 the working clock for the transmit system interface is sourced internally by the working clock of the receive system interface. sclkx is ignored. global configuration register (read/write) value after reset: 00 h vis masked interrupts visible 0 masked interrupt status bits are not visible in registers isr0-4. 1 masked interrupt status bits are visible in isr0-4, but they are not visible in registers gis and cis. sci status change interrupt 70 gcr vis sci ses ecmc pd (x46)
peb 22554 operational description e1 semiconductor group 142 09.98 0 interrupts will be generated either on coming or going of the internal interrupt source. 1 the following interrupts will be activated if enabled with detecting and recovering of the internal interrupt source: isr2.los , isr2.ais, isr3.lmfa16 ses select external second timer 0 internal second timer selected 1 external second timer selected ecmc error counter mode cofa 0 the sa6 bit error indications are accumulated in the error counter cec3l/h. 1 a change of frame or multiframe alignment cofa is detected since the last re-synchronization. the events are accumulated in the error counter cec3l.1-0. multiframe periods received in the asynchronous state are accumulated in the error counter cec3l.7-2. an overflow of each counter is disabled. pd power down switches the appropriate single falc(1-4) between power up and power down mode. 0 power up 1 power down all outputs are driven inactive, except the multifunction ports, which are driven high. errored second mask (read/write) value after reset: ff h esm errored second mask this register functions as an additional mask register for the interrupt status bit errored second (isr3.es). a 1 in a bit position of esm sets the mask active for the interrupt status. 70 esm lfa fer cer ais los cve slip ebe (x47)
peb 22554 operational description e1 semiconductor group 143 09.98 disable error counter (write) value after reset: 00 h drbd disable receive buffer delay this bit has to be set before reading the register rbd. it will be automatically reset if rbd has been read. dcec3 disable crc error counter 3 dcec2 disable crc error counter 2 dcec1 disable crc error counter debc disable errored block counter dcvc disable code violation counter dfec disable framing error counter these bits are only valid if fmr1.ecm is cleared. they have to be set before reading the error counters. they will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of these bits the error counters are latched and then cleared. 70 dec drbd dcec3 dcec2 dcec1 debc dcvc dfec (x60)
peb 22554 operational description e1 semiconductor group 144 09.98 transmit cas register (write) value after reset: not defined transmit cas register 1-16 the transmit cas register access is enabled by setting bit xsp.casen = 1. each register except xs1 contains the cas bits for two timeslots. with the transmit multiframe begin isr1.xmb the contents of these registers will be copied into a shadow register. the contents will subsequently sent out in the timeslots 16 of the outgoing data stream. if isr1.xmb is not used and the write access to these registers is done exact in that moment when this interrupt is generated, data may be lost. xs1.7 will be sent out first and xs16.0 will be sent last. the transmit multiframe begin interrupt (xmb) requests that these registers should be serviced. if requests for new information are ignored, current contents will be repeated. xs1 has to be programmed with the multiframe pattern. this pattern should always stay low otherwise the remote end will lose its synchronization. with setting the y-bit a remote alarm will be transmitted to the far end. the x bits (spare bits) should be set to one if they are not used. if access to these registers is done without control of the interrupt isr1.xmb the registers should be write twice to avoid a internally data transfer error. 70 xs1 0 0 0 0 x y x x (x70) xs2 a1 b1 c1 d1 a16 b16 c16 d16 (x71) xs3 a2 b2 c2 d2 a17 b17 c17 d17 (x72) xs4 a3 b3 c3 d3 a18 b18 c18 d18 (x73) xs5 a4 b4 c4 d4 a19 b19 c19 d19 (x74) xs6 a5 b5 c5 d5 a20 b20 c20 d20 (x75) xs7 a6 b6 c6 d6 a21 b21 c21 d21 (x76) xs8 a7 b7 c7 d7 a22 b22 c22 d22 (x77) xs9 a8 b8 c8 d8 a23 b23 c23 d23 (x78) xs10 a9 b9 c9 d9 a24 b24 c24 d24 (x79) xs11 a10 b10 c10 d10 a25 b25 c25 d25 (x7a) xs12 a11 b11 c11 d11 a26 b26 c26 d26 (x7b) xs13 a12 b12 c12 d12 a27 b27 c27 d27 (x7c) xs14 a13 b13 c13 d13 a28 b28 c28 d28 (x7d) xs15 a14 b14 c14 d14 a29 b29 c29 d29 (x7e) xs16 a15 b15 c15 d15 a30 b30 c30 d30 (x7f)
peb 22554 operational description e1 semiconductor group 145 09.98 note: a software reset (cmdr.xres) will reset these registers. port configuration 1-4 (read/write) value after reset: 00 h rpc2 ...0 receive multifunction port configuration the multifunction ports rp(a-d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. the input function sypr may only be selected once, it should not be selected twice or more. register pc1 configures port rpa,while pc2 --> port rpb, pc3 --> port rpc and pc4 --> port rpd. 000sypr : synchronous pulse receive (input) together with register rc1/0 sypr defines the frame begin on the receive system interface. because of the offset programming the sypr and the rfm pin function could not be selected in parallel. 001rfm : receive frame sync (output) cmr2.irsp = 0: this receive frame marker could be active high for a 2.048 mhz period during any bit position of the current frame. programming is done with registers rc1/0. the internal time-slot assigner is disabled. cmr2.irsp = 1: internal generated frame synchronization pulse generated by the dco-r circuitry. together with registers rc1/0 the frame begin on the receive system interface is defined. this frame synchronization pulse is active low 2.048 mhz period. 010rmfb : receive multiframe begin (output) marks the beginning of every received multiframe or optionally the begin of every cas multiframe begin (active high). 011rsigm : receive signaling marker (output) marks the time-slots which are defined by register rtr1-4 of every frame at port rdo. 70 pc1 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x80) pc2 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x81) pc3 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x82) pc4 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x83)
peb 22554 operational description e1 semiconductor group 146 09.98 100rsig : receive signaling data (output) the received cas multiframe is transmitted on this pin. time- slots on rsig correlates directly to the time-slot assignment on rdo. in system interface multiplex mode all four received signaling data streams are merged into a single rail data stream byte or bit interleaved on rsig1. 101dlr : data link bit receive (output) marks the sa8-4 bits within the data stream on rdo. 110freez : freeze signaling (output) the freeze signaling status is active high by detecting a loss of signal alarm, or a loss of cas frame alignment or a receive slip (pos. or neg.). it will hold high for at least one complete multiframe after the alarm disappears. setting sic2.ffs enforces a high on pin freez. 111rfsp : receive frame synchronous pulse (output) marks the frame begin in the receivers synchrounous state. this marker is active low for 488 ns with a frequency of 8 khz. xpc2 ...0 transmit multifunction port configuration the multifunction ports xp(a-d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. each of the four different input functions ( sypx , xmfs, xsig, tclk ) may only be selected once. no input function should be selected twice or more. sypx and xmfs should not be selected in parallel. register pc1 configures port xpa,while pc2 --> port xpb, pc3 --> port xpc and pc4 --> port xpd. 000sypx : synchronous pulse transmit (input) together with register xc1/0 sypx defines the frame begin on the transmit system interface ports xdi and xsig. 001xmfs : transmit multiframe synchronization (input) together with register xc1/0 xmfs defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. 010xsig : transmit signaling data (input) input for transmit signaling data received from the signaling highway. in system interface multiplex mode latching of the data stream containing the 4 signaling multiframes is done byte or bit interleaved on port xdi1. optionally sampling of xsig data is controlled by the active high xsigm marker.
peb 22554 operational description e1 semiconductor group 147 09.98 011tclk : transmit clock (input) a 2.048 / 8.192 mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) should not be used. optionally this input functions as a synchronization clock for the dco-x circuitry with a frequencyof 2.048 mhz. 100xmfb : transmit multiframe begin (output) marks the beginning of every transmit multiframe. 101xsigm : transmit signaling marker (output) marks the time-slots which are defined by register ttr1-4 of every frame at port xdi. 110dlx : data link bit transmit (output) marks the sa8-4 bits within the data stream on xdi. 111xclk : transmit line clock (output) frequency: 2.048 mhz port configuration 5 (read/write) value after reset: 00 h cxmfs configure xmfs port 0 port xmfs is active low. 1 port xmfs is active high. csxp configure sclkx port 0 sclkx : input 1 sclkx : output csrp configure sclkr port 0 sclkr : input 1 sclkr : output crp configure rclk port 0 rclk : input 1 rclk : output 70 pc5 cxmfs csxp csrp crp (x84)
peb 22554 operational description e1 semiconductor group 148 09.98 global port configuration 1 (read/write) value after reset: 00 h smm system interface multiplex mode setting this bit enables a single rail data stream of 16.384 or 8.192 mbit/s containg all four e1 frames. the receive system interface for all four channels is running with the clock provided on sclkr1 and the frame sync pulse provided on sypr1 . the transmit system interface is running with sclkx1 and sypx1 . data will be transmitted / accepted in a byte or bit interleaved format. in the system interface multiplex mode the following pin configuration has to be fulfilled and must be identically for all for 4 channels: - sypr1 has to be provided on pin rpa1 - sypx1 has to be provided on pin xpa1 or - xmfs has to be provided on pin xpb1 - xsig has to be provided on pin xpc1 - rsig will be output on pin rpb1 each of the four channels have to be configured equally: - clocking rate : 16.384 or 8.192 mhz , sic1.ssc1/0 - data rate : 16.384 or 8.192 mbit/s, sic1.ssd, fmr1.ssd0 - time-slot offset programming : rc1/0 , xc1/0 - receive buffer size : sic1.rbs1/0 = 00 (2 frames) e.g. : system clock rate = 8.192 mhz : sic1.ssc1/0 = 10 and system data rate = 8.192 mbit/s : sic1.ssd1 = 1 , fmr1.ssd0 = 0 the multiplexed data stream is internal logically ored. therefore the selection of the active channel phase have to be configured different for each single channel falc(1-4). programming is done with sic2.sics2-0. for falc1: sic2.sics2-0 = 000, selects the first channel phase for falc2: sic2.sics2-0 = 001, selects the second channel phase for falc3: sic2.sics2-0 = 010, selects the third channel phase for falc4: sic2.sics2-0 = 011, selects the fourth channel phase byte interleaved data format: sic1.bim = 0 xdi/rdo: f1-ts0, f2-ts0, f3-ts0, f4-ts0, f1-ts1, ... f4-ts31 x/rsig: f1-sts0, f2-sts0, f3-sts0, f4-sts0, f1-... f4-sts31 70 gpc1 smm csfp1 csfp0 fss1 fss0 r1s1 r1s0 (85)
peb 22554 operational description e1 semiconductor group 149 09.98 or : bit interleaved data format: sic1.bim = 1 xdi/rdo: f1-ts0-b1, f2-ts0-b1, f3-ts0-b1, f4-ts0-b1, f1-ts0- b2, ... f4-ts31-b8 x/rsig: f1-sts0-b1, f2-sts0-b1, f3-sts0-b1, f4-sts0-b1, f1- sts0-b2, ... f4-sts31-b8 with : f = framer, ts = time-slot, sts = signaling time-slot, b = bit in system interface multiplex mode signals on rdo2-4 and rsig2-4 are undefined, while signals on sclkr2-4, sypr 2-4, sclkx2-4, sypx 2-4, xdi2-4 and xsig2-4 are ignored. csfp1 ... 0 configure sec / fsc port the fsc pulse is generated if the dco-r circuitry of the selected channel is active (cmr2.irsc = 1 or cmr1.rs1/0 = 10 or 11). 00 sec : input , active high 01 sec : output, active high 10 fsc: output , active high 11 fsc: output, active low fss1 ... 0 sec / fsc source one of the four internal generated dejittered 8 khz clocks or second timers (sec) are output on port sec / fsc. gpc1.csfp1 = 1: 00 fsc : 8 khz sourced by channel 1 01 fsc : 8 khz sourced by channel 2 10 fsc : 8 khz sourced by channel 3 11 fsc : 8 khz sourced by channel 4 gpc1.csfp1 = 0: 00 sec : second timer sourced by channel 1 01 sec: second timer sourced by channel 2 10 sec: second timer sourced by channel 3 11 sec: second timer sourced by channel 4
peb 22554 operational description e1 semiconductor group 150 09.98 r1s1 ... 0 rclk1 source one of the four internal generated receive route clocks are output on port rclk1. outputs rclk2-4 are valid independent of these bits. refer to bit cmr1.rs1/0. 00 extracted receive clock of channel 1 01 extracted receive clock of channel 2 10 extracted receive clock of channel 3 11 extracted receive clock of channel 4
peb 22554 operational description e1 semiconductor group 151 09.98 4.5 status register description table 12 status registeraddress arrangement address register type comment 00 100 200 300 rfifo r receive fifo 49 149 249 349 rbd r receive buffer delay 4a vstr r version status 4b 14b 24b 34b res r receive equalizer status 4c 14c 24c 34c frs0 r framer receive status 0 4d 14d 24d 34d frs1 r framer receive status 1 4e 14e 24e 34e rsw r receive service word 4f 14f 24f 34f rsp r receive spare bits 50 150 250 350 fecl r framing error counter low 51 151 251 351 fech r framing error counter high 52 152 252 352 cvcl r code violation counter low 53 153 253 353 cvch r code violation counter high 54 154 254 354 cec1l r crc error counter 1 low 55 155 255 355 cec1h r crc error counter 1 high 56 156 256 356 ebcl r e-bit error counter low 57 157 257 357 ebch r e-bit error counter high 58 158 258 358 cec2l r crc error counter 2 low 59 159 259 359 cec2h r crc error counter 2 high 5a 15a 25a 35a cec3l r crc error counter 3 low 5b 15b 25b 35b cec3h r crc error counter 3 high 5c 15c 25c 35c rsa4 r receive sa4 bit register 5d 15d 25d 35d rsa5 r receive sa5 bit register 5e 15e 25e 35e rsa6 r receive sa6 bit register 5f 15f 25f 35f rsa7 r receive sa7 bit register 60 160 260 360 rsa8 r receive sa8 bit register 61 161 261 361 rsa6s r receive sa6 bit status register 62 162 262 362 rsp1 r/w receive signaling pointer 1 63 163 263 363 rsp2 r/w receive signaling pointer 2
peb 22554 operational description e1 semiconductor group 152 09.98 64 164 264 364 sis r signaling status register 65 165 265 365 rsis r receive signaling status register 66 166 266 366 rbcl r receive byte control low 67 167 267 367 rbch r receive byte control high 68 168 268 368 isr0 r interrupt status register 0 69 169 269 369 isr1 r interrupt status register 1 6a 16a 26a 36a isr2 r interrupt status register 2 6b 16b 26b 36b isr3 r interrupt status register 3 6c 16c 26c 36c isr4 r interrupt status register 4 6d 16d 26d 36d 6e 16e 26e 36e gis r global interrupt status 6f cis r channel interrupt status 70 170 270 370 rs1 r receive cas register 1 71 171 271 371 rs2 r receive cas register 2 72 172 272 372 rs3 r receive cas register 3 73 173 273 373 rs4 r receive cas register 4 74 174 274 374 rs5 r receive cas register 5 75 175 275 375 rs6 r receive cas register 6 76 176 276 376 rs7 r receive cas register 7 77 177 277 377 rs8 r receive cas register 8 78 178 278 378 rs9 r receive cas register 9 79 179 279 379 rs10 r receive cas register 10 7a 17a 27a 37a rs11 r receive cas register 11 7b 17b 27b 37b rs12 r receive cas register 12 7c 17c 27c 37c rs13 r receive cas register 13 7d 17d 27d 37d rs14 r receive cas register 14 7e 17e 27e 37e rs15 r receive cas register 15 7f 17f 27f 37f rs16 r receive cas register 16 table 12 status registeraddress arrangement
peb 22554 operational description e1 semiconductor group 153 09.98 receive fifo (read) rfifo reading data from rfifo can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft 1 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). data transfer up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4, 2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the receive message complete command (rmc). receive buffer delay (read) rbd5rbd0... receive elastic buffer delay these bits informs the user about the current delay (in time-slots) through the receive elastic buffer. the delay is updated every 512 or 256 bits (sic1.rbs1/0). before reding this register the user has to set bit dec.drbd in order to halt the current value of this register. after reading rbd updating of this register is enabled. not valid if the receive buffer is bypassed. 000000 = delay < 1 time-slot : : 111111 = delay >63 time-slots 70 rfifo rf7 rf0 (x00/x01) 70 rbd rbd5 rbd4 rbd3 rbd2 rbd1 rbd0 (x49)
peb 22554 operational description e1 semiconductor group 154 09.98 version status register (read) vn7 C vn0 version number of chip 00 h version 1.1 receive equalizer status (read) ev1ev0... equalizer status valid these bits informs the user about the current state of the receive equalization network. only valid if lim1.eqon is set. 00 equalizer status not valid, still adapting 01 equalizer status valid 10 equalizer status not valid 11 equalizer status valid but high noise floor res4res0... receive equalizer status the current line attenuation status in steps of nearly 1.7 db are displayed in these bits. only valid if bits ev1/0 = 01. accuracy: +/- 2 digit, based on temperature influence and noise amplitude variations. 00000 attenuation: 0 db ... 11001 max. attenuation: -34 db framer receive status register 0 (read) los loss of signal detection: this bit is set when the incoming signal has no transitions (analog 70 vstr vn7 vn0 (4a) 70 res ev1 ev0 res4 res3 res2 res1 res0 (x4b) 70 frs0 los ais lfa rra nmf lmfa (x4c)
peb 22554 operational description e1 semiconductor group 155 09.98 interface) or logical zeros (dig. interface) in a time interval of t consecutive pulses, where t is programmable via pcd register. total account of consecutive pulses: 16 < t < 4096. analog interface: the receive signal level where no transition will be declared is defined by the programmed value of lim1.ril2-0. recovery: analog interface: the bit will be reset in short haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril2-0) for at least m pulse periods defined by register pcr in the pcd time interval. in long haul mode addtionally bit res.6 must be set for at least 250sec. digital interface: the bit will be reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) will be set.. the bit will also be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. ais alarm indication signal the function of this bit is determined by fmr0.alm. fmr0.alm = 0: this bit is set when two or less zeros in the received bit stream are detected in a time interval of 250 m s and the quadfalc is in the asynchronous state (frs0.lfa = 1). the bit will be reset when no alarm condition is detected (etsi). fmr0.alm = 1: this bit is set when the incoming signal has two or less zeros in each of two consecutive double frame period (512 bits). this bit will be cleared when each of two consecutive doubleframe periods contain three or more zeros or when the frame alignment signal fas has been found. (itu-t: g.775) the bit will also be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. with the rising edge of this bit an interrupt status bit (isr2.ais) will be set. lfa loss of frame alignment
peb 22554 operational description e1 semiconductor group 156 09.98 this bit is set after detecting 3 or 4 consecutive incorrect fas words or 3 or 4 consecutive incorrect service words (can be disabled). with the rising edge of this bit an interrupt status bit (isr2.lfa) will be set. the specification of the loss of sync conditions is done via bits rc1.swd and rc1.asy4. after loss of synchronization, the frame aligner will resynchronize automatically. the following conditions have to be detected to regain synchronous state: C the presence of the correct fas word in frame n. C the presence of the correct service word (bit 2 = 1) in frame n + 1. C for a second time the presence of a correct fas word in frame n+2. the bit is cleared when synchronization has been regained (directly after the second correct fas word of the procedure described above has been received). if the crc-multiframe structure is enabled by setting bit fmr2.rfs1, multiframe alignment is assumed to be lost if pulse-frame synchronization has been lost. the resynchronization procedure for multiframe alignment starts after the bit frs0.lfa has been cleared. multiframe alignment has been regained if two consecutive crc- multiframes have been received without a framing error (refer to frs0.lmfa). the bit will be set during alarm simulation and reset if fmr0.sim is cleared and no alarm condition exists. if bit frs0.lfa is cleared a loss of frame alignment recovery interrupt status isr2.far will be generated. rra receive remote alarm set if bit 3 of the received service word is set. an alarm interrupt status isr2.ra can be generated if the alarm condition is detected. frs0.rra will be cleared when no alarm is detected. at the same time a remote alarm recovery interrupt status isr2.rar will be generated. the bit rsw.rra has the same function. both status and interrupt status bits will be set during alarm simulation.
peb 22554 operational description e1 semiconductor group 157 09.98 nmf no multiframe alignment found this bit is only valid if the crc4 interworking is selected (fmr2.rfs1/0 = 11). set if the multiframe pattern could not be detected in a time interval of 400 msec after the framer has reached the doubleframe synchronous state. the receiver is then automatically switched to doubleframe format. this bit is reset if the basic framing has been lost. lmfa loss of multiframe alignment not used in doubleframe format (fmr2.rfs1 = 0). in this case, set to logical 1. in crc-multiframe mode (fmr2.rfs1 = 1), this bit is set C if force resynchronization is initiated by setting bit fmr0.frs, or C if multiframe force resynchronization is initiated by setting bit fmr1.mfcs, or C if pulseframe alignment has been lost (frs0.lfa). it is reset if two crc-multiframes have been received at an interval of n 2 ms (n = 1, 2, 3) without a framing error. if bit frs0.lmfa is cleared a loss of multiframe alignment recovery interrupt status isr2.mfar will be generated. framer receive status register 1 (read) ts16ra receive timeslot 16 remote alarm this bit contains the actual information of the received remote alarm bit rs1.2 in time-slot 16. setting and resetting of this bit will cause an interrupt status change isr3.ra16. ts16los receive timeslot 16 loss of signal this bit is set if the incoming ts16 data stream contains always zeros for at least 16 contiguously received time-slots. a one in a time-slot 16 will reset this bit. 7 0 frs1 ts16ra ts16los ts16ais ts16lfa xls xlo (x4d)
peb 22554 operational description e1 semiconductor group 158 09.98 ts16ais receive timeslot 16 alarm indication signal the detection of the alarm indication signal in timeslot 16 is according to itu-t g.775. this bit is set if the incoming ts16 contains less than 4 zeros in each of two consecutive ts16 multiframe periods. this bit will be cleared if two consecutive received cas multiframe periods contains more than 3 zeros or the multiframe pattern was found in each of them. this bit will be cleared if ts0 synchronization is lost. ts16lfa receive timeslot 16 loss of multiframe alignment 0 ... the cas controller is in synchronous state after frame alignment is accomplished. 1 ... this bit is set if the framing pattern 0000 in 2 consecutive cas multiframes were not found or in all ts16 of the preceding multiframe all bits were reset. an interrupt isr3.lmfa16 will be generated. xls transmit line short significant only if the ternary line interface is selected by lim1.drs=0. 0 normal operation. no short is detected. 1 the xl1 and xl2 are shortend for at least 3 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high impedance state if bit xpm2.daxlt is reset. after 128 consecutive pulse periods the outputs xl1/2 are activated again and the internal transmit current limiter is checked. if a short between xl1/2 is still further active the outputs xl1/2 are in high impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit will be reset. with any change of this bit an interrupt isr1.xlsc will be generated. in case of xpm2.xlt is set this bit will be frozen. xlo transmit line open 0 normal operation 1 this bit will be set if at least 32 consecutive zeros were sent via pins xl1/xl2 resp. xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc will be set. in case of xpm2.xlt is set this bit will be frozen.
peb 22554 operational description e1 semiconductor group 159 09.98 receive service word pulseframe (read) rsi receive spare bit for international use first bit of the received service word. it is fixed to one if crc- multiframe mode is enabled. rra receive remote alarm equivalent to bit frs0.rra. ry0ry4 receive spare bits for national use (y-bits, sn-bits, sa-bits) receive spare bits/additional status (read) si1si2 submultiframe error indication 1, 2 not valid if doubleframe format is enabled. in this case, both bits are set to logical 1. when using crc-multiframe format these bits are set to 0 if multiframe alignment has been lost, or if the last multiframe has been received with crc error(s). si1 flags a crc error in last sub-multiframe 1, si2 flags a crc error in last sub-multiframe 2. 1 ... if at multiframe synchronous state last assigned sub-multiframe has been received without a crc error. both flags will be actualized with beginning of every received crc multiframe. if automatic transmission of sub-multiframe status is enabled by setting bit xsp.axs, above status information will be inserted automatically in s i -bit position of every outgoing crc multiframe (under the condition that time-slot 0 transparent modes are both disabled): si1 ? s i -bit of frame 13, si2 ? s i -bit of frame 15. 70 rsw rsi rra ryo ry1 ry2 ry3 ry4 (x4e) 70 rsp si1 si2 llbdd llbad rsif rs13 rs15 (x4f)
peb 22554 operational description e1 semiconductor group 160 09.98 llbdd line loop back deactuation signal detected this bit is set to one in case the llb deactuate signal is detected and then received over a period of more than 25 msec with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the timeslot 0 is not taken into account for the error rate calculation. any change of this bit will cause a llbsc interrupt. llbad line loop back actuation signal detected depending on bit lcr1.eprm the source of this status bit changed. lcr1.eprm=0: this bit is set to one in case the llb actuate signal is detected and then received over a period of more than 25 msec with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the timeslot 0 is not taken into account for the error rate calculation. any change of this bit will cause a llbsc interrupt. prbs status lcr1.eprm=1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a ber 1/10. a data stream containing all zeros with / without framing bits is also a valid pseudo random bit sequence. rsif receive spare bit for international use (fas word) first bit in fas-word. used only in doubleframe format, otherwise fixed to 1. rs13 receive spare bit (frame 13, crc multiframe) first bit in service word of frame 13. significant only in crc- multiframe format, otherwise fixed to 0. this bit is updated with beginning of every received crc multiframe. rs15 receive spare bit (frame 15, crc multiframe) first bit in service word of frame 15. significant only in crc- multiframe format, otherwise fixed to 0. this bit is updated with beginning of every received crc multiframe.
peb 22554 operational description e1 semiconductor group 161 09.98 framing error counter (read) fe15fe0 framing errors this 16-bit counter will be incremented when a fas word has been received with an error. framing errors will not be counted during asynchronous state. during alarm simulation, the counter is incremented every 250 m s up to its saturation. the error counter will not roll over. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dfec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (x50) 70 fech fe15 fe8 (x51)
peb 22554 operational description e1 semiconductor group 162 09.98 code violation counter (read) cv15cv0 code violations no function if nrz code has been enabled. if the hdb3 or the cmi code is selected, the 16-bit counter will be incremented when violations of the hdb3 code are detected. the error detection mode is determined by programming the bit fmr0.extd. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. the error counter will not roll over. during alarm simulation, the counter is incremented every four bits received up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcvc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (x52) 70 cvch cv15 cv8 (x53)
peb 22554 operational description e1 semiconductor group 163 09.98 crc error counter 1 (read) cr15cr0 crc errors no function if doubleframe format is selected. in crc-multiframe mode, the 16-bit counter will be incremented when a crc-submultiframe has been received with a crc error. crc errors will not be counted during asynchronous state. the error counter will not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec1 has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec1 will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec1l cr7 cr0 (x54) 70 cec1h cr15 cr8 (x55)
peb 22554 operational description e1 semiconductor group 164 09.98 e bit error counter (read) eb15eb0 e-bit errors if doubleframe format is selected, febeh/l has no function. if crc- multiframe mode is enabled, febeh/l works as submultiframe error indication counter (16 bits) which counts zeros in si-bit position of frame 13 and 15 of every received crc multiframe. the error counter will not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.debc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl eb7 eb0 (x56) 70 ebch eb15 eb8 (x57)
peb 22554 operational description e1 semiconductor group 165 09.98 crc error counter 2 (read) cc15cc0 crc error counter (reported from te via sa6 -bit) depending of bit lcr1.eprm the error counter increment is selected: lcr1.eprm=0: if doubleframe format is selected, cec2h/l has no function. if crc- multiframe mode is enabled, cec2h/l works as sa6 bit error indication counter (16 bits) which counts the sa6 bit sequence 0001 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. sa6 bit sequence: sa61, sa62, sa63, sa64 = 0001 or 0011 where sa61 is received in frame 1 or 9 in every multiframe. pseudo random bit sequence error counter lcr1.eprm=1: this 16-bit counter will be incremented with every received prbs bit error in the prbs synchronous state frs1.llbad = 1. the error counter will not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec2 has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec2 will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cec2l cc7 cc0 (x58) 70 cec2h cc15 cc8 (x59)
peb 22554 operational description e1 semiconductor group 166 09.98 crc error counter 3 (read) ce15ce0 crc error counter (detected at t ref. point via sa6 -bit) gcr.ecmc = 0 : if doubleframe format is selected, cec3h/l has no function. if crc-multiframe mode is enabled, cec3h/l works as sa6 bit error indication counter (16 bits) which counts the sa6 bit sequence 0010 and 0011in every received crc submultiframe. incrementing the counter is only possible in the multiframe synchronous state frs0.lmfa = 0. sa6 bit sequence: sa61, sa62, sa63, sa64 = 0010 or 0011 where sa61 is received in frame 1 or 9 in every multiframe. the error counter will not roll over. during alarm simulation, the counter is incremented once per submultiframe up to its saturation. ce7ce2 multiframe counter gcr.ecmc = 1 : this 6 bit counter increments with each multiframe period in the asynchronous state frs0.lfa/lmfa =1. during alarm simulation, the counter is incremented once per multiframe up to its saturation. ce1ce0 change of frame alignment counter gcr.ecmc = 1 : this 2 bit counter increments with each detected change of frame / multiframe alignment. the error counter will not roll over. during alarm simulation, the counter is incremented once per multiframe up to its saturation. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec3 has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec3 will automatically be reset with reading the error counter high byte. 70 cec3l ce7 ce0 (x5a) 70 cec3h ce15 ce8 (x5b)
peb 22554 operational description e1 semiconductor group 167 09.98 if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. receive sa4-bit register (read) rs47rs40 receive sa4-bit data (y-bits) rs57rs50 receive sa5-bit data rs67rs60 receive sa6-bit data rs77rs70 receive sa7-bit data rs87rs80 receive sa8-bit data this register contains the information of the eight sax bits (x = 4 - 8) of the previously received crc multiframe. these registers will be updated with every multiframe begin interrupt isr0.rmb. rs40 is received in bit-slot 4 of every service word in frame 1, rs47 in frame 15 rs50 is received in bit-slot 5, time-slot 0, frame 1, rs57 in frame 15 rs60 is received in bit-slot 6, time-slot 0, frame 1, rs67 in frame 15 rs70 is received in bit-slot 7, time-slot 0, frame 1, rs77 in frame 15 rs80 is received in bit-slot 8, time-slot 0, frame 1, rs87 in frame 15 valid if crc multiframe format is enabled by setting bits fmr2.rfs1 = 1 or fmr2.rfs1/0 = 01 (doubleframe format). 70 rsa4 rs47 rs40 (x5c) rsa5 rs57 rs50 (x5d) rsa6 rs67 rs60 (x5e) rsa7 rs77 rs70 (x5f) rsa8 rs87 rs80 (x60)
peb 22554 operational description e1 semiconductor group 168 09.98 receive sa6-bit status (read) four consecutive received sa6-bits are checked on the by ets 300233 defined sa6-bit combinations. the quadfalc will detect the following fixed sa6-bit combinations: sa61,sa62,sa63,sa64=1000; 1010; 1100; 1110; 1111. all other possible 4 bit combinations are grouped to status x. a valid sa6-bit combination must occur three times in a row. the corresponding status bit in this register will be set. even if the detected status will be active for a short time the status bit remains active until this register is read. reading the register will reset all pending status information. with any change of state of the sa6-bit combinations an interrupt status isr0.sa6sc will be generated. during the basicframe asynchronous state updating of this register and interrupt status isr0.sa6sc is disabled. in multiframe format the detection of the sa6-bit combinations can be done either synchronous or asynchronous to the submultiframe (fmr3.sa6sy). in synchronous detection mode updating of register rsa6s is done in the multiframe synch. state (frs0.lmfa=0). in asynchr. detection mode updating is independent to the multiframe synchronous state. s_x receive sa6-bit status_x if none of the fixed sa6-bit combinations are detected this bit will be set. s_f receive sa6-bit status: 1111 receive sa6-bit status 1111 is detected for three times in a row in the sa6-bit positions. s_e receive sa6-bit status: 1110 receive sa6-bit status 1110 is detected for three times in a row in the sa6-bit positions. s_c receive sa6-bit status: 1100 receive sa6-bit status 1100 is detected for three times in a row in the sa6-bit positions. s_a receive sa6-bit status: 1010 70 rsa6s s_x s_f s_e s_c s_a s_8 (x61)
peb 22554 operational description e1 semiconductor group 169 09.98 receive sa6-bit status 1010 is detected for three times in a row in the sa6-bit positions. s_8 receive sa6-bit status: 1000 receive sa6-bit status 1000 is detected for three times in a row in the sa6-bit positions. receive signaling pointer 1 (read) value after reset: 00 h rs8crs1c receive signaling register rs1-8 changed a one in each bit position indicates that the received signaling data in the corresponding rs1-8 registers are updated. bit rs1c is the pointer for register rs1,... while rs8c points to rs8. receive signaling pointer 2 (read) value after reset: 00 h rs16crs9c receive signaling register rs9-16 changed a one in each bit position indicates that the received signaling data in the corresponding rs9-16 registers are updated. bit rs9c is the pointer for register rs9,... while rs16c points to rs16. signaling status register (read) xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres 70 rsp1 rs8c rs7c rs6c rs5c rs4c rs3c rs2c rs1c (x62) 70 rsp2 rs16c rs15c rs14c rs13c rs12c rs11c rs10c rs9c (x63) 70 sis xdov xfw xrep rli cec sfs (x64)
peb 22554 operational description e1 semiconductor group 170 09.98 C or when all bytes in the accessible half of the xfifo have been moved in the inaccessible half. xfw transmit fifo write enable data can be written to the xfifo. xrep transmission repeat status indication of cmdr.xrep. rli receive line inactive neither flags as interframe time fill nor frames are received via the signaling timeslot. cec command executing 0 no command is currently executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 2.5 periods of the current system data rate. sfs status freeze signaling 0 freeze signaling status inactive. 1 freeze signaling status active receive signaling status register (read) rsis relates to the last received hdlc frame; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr valid frame determines whether a valid frame has been received. 1 valid 0 invalid an invalid frame is either C a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or 70 rsis vfr rdo crc16 rab ha1 ha0 la (x65)
peb 22554 operational description e1 semiconductor group 171 09.98 C a frame which is too short taking into account the operation mode selected via mode (mds2-0) and the selection of receive crc on/off (ccr2.rcrc) as follows: ? mds2-0 = 011 (16 bit address), rcrc = 0 : 4 bytes; rcrc = 1 : 3-4 bytes ? mds2-0 = 010 (8 bit address), rcrc = 0 : 3 bytes; rcrc = 1 : 2-3 bytes note: shorter frames are not reported. rdo receive data overflow a rfifo data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16 crc16 compare/check 0 crc check failed; received frame contains errors. 1 crc check o.k.; received frame is error-free. rab receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. ha1, ha0 high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the quadfalc compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: 00 rah2 has been recognized 01 broadcast address has been recognized 10 rah1 has been recognized c/r = 0 (bit 1) 11 rah1 has been recognized c/r = 1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by 10 or 11.
peb 22554 operational description e1 semiconductor group 172 09.98 la low byte address compare significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 ral2 has been recognized 1 ral1 has been recognized receive byte count low (read) together with rbch (bits rbc11 - rbc8), indicates the length of a received frame (14095 bytes). bits rbc4-0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. received byte count high (read) value after reset: 000 xxxxx ov counter overflow more than 4095 bytes received. rbc11 C rbc8receive byte count (most significant bits) together with rbcl (bits rbc7rbc0) indicate the length of the received frame. 70 rbcl rbc7 rbc0 (x66) 70 rbch ov rbc11 rbc8 (x67)
peb 22554 operational description e1 semiconductor group 173 09.98 interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit gcr.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc4C0. additional information is available in the rsis register. rfs receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs interrupt, the contents of ? ral1 ? rsis - bits 3-1 are valid and can be read by the cpu. t8ms receive time out 8 msec only active if multiframing is enabled. the framer has found the doubleframing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt will be set to indicate that no multiframing could be found within a time window of 8 msec. in multiframe synchronous state this interrupt will be not generated. refer also to floating multiframe alignment window. 70 isr0 rme rfs t8ms rmb casc crc4 sa6sc rpf (x68)
peb 22554 operational description e1 semiconductor group 174 09.98 rmb receive multiframe begin this bit is set with the beginning of a received crc multiframe related to the internal receive line timing. in crc multiframe format fmr2.rfs1 = 1 or in doubleframe format fmr2.rfs1/0 = 01 this interrupt occurs every 2 msec. if fmr2.rfs1/0 = 00 this interrupt will be generated every doubleframe (512 bits). casc received cas information changed this bit is set with the updating of a received cas multiframe information in the registers rs1-16. if the last received cas information changed from the previous received updating is started. this interrupt will only occur in the ts0 and ts16 synchronous state. the registers rs1-16 should be read within the next 2 ms otherwise the contents may be lost. crc4 receive crc4 error 0... no crc4 error occurs. 1... the crc4 check of the last received submultiframe failed. sa6sc receive sa6-bit status changed with every change of state of the received sa6-bit combinations this interrupt will be set. rpf receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. interrupt status register 1 (read) all bits are reset when isr1 is read. if bit gcr.vis is set to 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. llbsc line loop back status change depending on bit lcr1.eprm the source of this interrupt status changed: 70 isr1 llbsc rdo alls xdu xmb xlsc xpr (x69)
peb 22554 operational description e1 semiconductor group 175 09.98 lcr1.eprm=0: this bit is set to one, if the llb actuate signal or the llb deactuate signal, resp., is detected over a period of 25 msec with a bit error rate less than 1/100. the llbsc bit is also set to one, if the current detection status is left, i.e., if the bit error rate exceeds 1/100. the actual detection status can be read from the rsp.llbad and rsp.llbdd, resp. prbs status change lcr1.eprm=1: with any change of state of the prbs synchronizer this bit will be set. the current status of the prbs synchronizer is indicated in rsp.llbad. rdo receive data overflow this interrupt status indicates that the cpu does not respond quickly enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls all sent this bit is set if the last bit of the current frame is completely sent out and xfifo is empty. xdu transmit data underrun transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. xmb transmit multiframe begin this bit is set every 2 ms with the beginning of a transmitted multiframe related to the internal transmit line interface timing. just before setting this bit registers xs1-16 are copied in the transmit
peb 22554 operational description e1 semiconductor group 176 09.98 shift registers. the registers xs1-16 are empty and has to be updated otherwise the contents will be retransmitted. xlsc transmit line status change xlsc is set to one with the rising edge of the bit frs1.xlo or with any change of bit frs1.xls. the actual status of the transmit line monitor can be read from the frs1.xls and frs1.xlo. xpr transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit gcr.vis is set to 1, interrupt statuses in isr2 may be flagged although they are masked via register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far frame alignment recovery the framer has reached doubleframe synchronization. set when bit fsr0.lfa is reset. it is set also after alarm simulation is finished and the receiver is still synchron. lfa loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it will be set during alarm simulation. mfar multiframe alignment recovery set when the framer has found two crc-multiframes at an interval of n x 2 ms (n = 1, 2, 3, ) without a framing error. at the same time bit frs0.lmfa is reset. 70 isr2 far lfa mfar t400ms ais los rar ra (x6a)
peb 22554 operational description e1 semiconductor group 177 09.98 it is set also after alarm simulation is finished and the receiver is still synchron. only active if crc-multiframe format is selected. t400ms receive time out 400 msec only active if multiframing is enabled. the framer has found the doubleframing (basic framing) frs0.lfa = 0 and is searching for the multiframing. this interrupt will be set to indicate that no multiframing could be found within a time window of 400 msec after basic framing has been achieved. in multiframe synchronous state this interrupt will not be generated. ais alarm indication signal this bit is set when an alarm indication signal is detected and bit frs0.ais is set. it will be set during alarm simulation. if gcr.sci is set high this interrupt status bit will be set with every change of state of frs0.ais. los loss of signal this bit is set when a loss of signal alarm is detected in the received bitstream and frs0.los is set. it will be set during alarm simulation. if gcr.sci is set high this interrupt status bit will be set with every change of state of frs0.los. rar remote alarm recovery set if a remote alarm in ts0 is cleared and bit frs0.ra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra remote alarm set if a remote alarm in ts0 is detected and bit frs0.ra is set. it will be set during alarm simulation.
peb 22554 operational description e1 semiconductor group 178 09.98 interrupt status register 3 (read) all bits are reset when isr3 is read. if bit gcr.vis is set to 1, interrupt statuses in isr3 may be flagged although they are masked via register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. es errored second this bit is set if at least one enabled interrupt source via esm is set during the time interval of one second. interrupt sources of esm register: lfa = loss of frame alignment detected (frs0.lfa) fer = framing error received cer= crc error received ais = alarm indication signal (frs0.ais) los = loss of signal (frs0.los) cve = code violation detected slip= receive slip positive/negative detected ebe = e- bit error detected (rsp.rs13/15) sec second timer the internal one second timer has expired. the timer is derived from clock rclk. lmfa16 loss of multiframe alignment ts 16 multiframe alignment of timeslot 16 has been lost if two consecutive multiframe pattern are not detected or if in 16 consecutive timeslot 16 all bits are reset. if register gcr.sci is high this interrupt status bit will be set with every change of state of frs1.ts16lfa. ais16 alarm indication signal ts 16 status change the alarm indication signal ais in timeslot 16 for the 64 kbit/s channel associated signaling is detected or cleared. a change in bit frs1.ts16ais will set this interrupt. (this bit is set if the incoming ts 16 signal contains less than 4 zeros in each of two consecutive ts16- multiframe periods.) 70 isr3 es sec lmfa16 ais16 ra16 rsn rsp (x6b)
peb 22554 operational description e1 semiconductor group 179 09.98 ra16 remote alarm ts 16 status change a change in the remote alarm bit in cas multiframe alignment word is detected. rsn receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 2.048 mhz. a frame will be skipped. it will be set during alarm simulation. rsp receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 2.048 mhz. a frame will be repeated. it will be set during alarm simulation. interrupt status register 4 (read) all bits are reset when isr4 is read. if bit gcr.vis is set to 1, interrupt statuses in isr4 may be flagged although they are masked via register imr4. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. xsp transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 2.048 mhz. a frame will be repeated. xsn transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 2.048 mhz. a frame will be skipped. 7 0 isr4 xsp xsn (x6c)
peb 22554 operational description e1 semiconductor group 180 09.98 global interrupt status register (read) value after reset: 00 h this status register points to pending interrupts sourced by isr4 ... isr0. channel interrupt status register (read) value after reset: 00 h this status register points to pending interrupts sourced by the gis registers of each channel. gis4 ... register gis of falc4 gis3 ... register gis of falc3 gis2 ... register gis of falc2 gis1 ... register gis of falc1 70 gis isr4 isr3 isr2 isr1 isr0 (x6e) 70 cis gis4gis3gis2gis1 (6f)
peb 22554 operational description e1 semiconductor group 181 09.98 receive cas register (read) value after reset: not defined receive cas register 1-16 each register except rs1 contains the received cas bits for two timeslots. the received cas multiframe will be compared with the previously received one. if the contents changed a cas multiframe changed interrupt (isr0.casc) is generated and informs the user that a new multiframe has to be read within the next 2 ms. if requests for reading the rs1-16 register are ignored, the received data may be lost. rs1 contains frame 0 of the cas multiframe. msb is received first. additionally a receive signaling data change pointer indicates an update of register rs1- 16 . refer also to register rsp1/2. access to rs1-16 registers is only valid if the serial receive signaling access on the system highway is disabled. 70 rs1 0 0 0 0 x y x x (x70) rs2 a1 b1 c1 d1 a16 b16 c16 d16 (x71) rs3 a2 b2 c2 d2 a17 b17 c17 d17 (x72) rs4 a3 b3 c3 d3 a18 b18 c18 d18 (x73) rs5 a4 b4 c4 d4 a19 b19 c19 d19 (x74) rs6 a5 b5 c5 d5 a20 b20 c20 d20 (x75) rs7 a6 b6 c6 d6 a21 b21 c21 d21 (x76) rs8 a7 b7 c7 d7 a22 b22 c22 d22 (x77) rs9 a8 b8 c8 d8 a23 b23 c23 d23 (x78) rs10 a9 b9 c9 d9 a24 b24 c24 d24 (x79) rs11 a10 b10 c10 d10 a25 b25 c25 d25 (x7a) rs12 a11 b11 c11 d11 a26 b26 c26 d26 (x7b) rs13 a12 b12 c12 d12 a27 b27 c27 d27 (x7c) rs14 a13 b13 c13 d13 a28 b28 c28 d28 (x7d) rs15 a14 b14 c14 d14 a29 b29 c29 d29 (x7e) rs16 a15 b15 c15 d15 a30 b30 c30 d30 (x7f)
semiconductor group 182 09.98 quad framing and line interface component for e1/t1 quadfalc peb 22554 cmos p-tqfp-144 type version ordering code package peb 22554-h v1.1 p-tqfp-144(smd) quadfalc in t1 / j1 mode 5 features t1 / j1 quad line interface ? high density, generic interface for all e1 / ds1 / dsx-1 / j1 applications ? analog receive and transmit circuitry for long / short haul applications ? data and clock recovery using an integrated digital phase locked loop ? maximum line attenuation up to -36 db at 772 khz adaptively controlled receive equalization network adjusts up to 6200 feet (pulp 22awg) in length, noise - and crosstalk -filter, line attenuation status ? programmable line build-out for csu signals according to ansi t1. 403+ fcc68 0db, -7.5db, -15db, -22.5 db ? low transmitter output impedance for high transmit return loss ? tri-state function of the analog transmit line outputs ? programmable transmit pulse shape ? transmit line monitor protecting the device from damage ? jitter specifications of itu-t i.431, g.703 and at&t tr 62411 met ? crystal-less wander and jitter attenuation/compensation ? low frequency reference clock: 1.544 mhz ? power down function per channel ? dual rail or single rail digital inputs and outputs ? unipolar nrz for interfacing fibre optical transmission routes ? selectable line codes (b8zs, ami with zcs) ? loss of signal indication with programmable thresholds according to itu-t g.775 and ansi t1. 403 ? clock generator for jitter free system / transmit clocks per channel ? local loop and remote loop for diagnostic purposes ? low power device , single power supply: 3.3 v
peb 22554 general features t1 semiconductor group 183 09.98 quad frame aligner ? frame alignment/synthesis for 1.544 mbit/s according to itu-t g.704 and jt g.704 ? programmable formats : 4-frame multiframe (f4, ft), 12-frame multiframe (f12, d3/4), extended superframe (esf), remote switch mode (f72, slc96) ? selectable conditions for recover and loss of frame alignment ? performs synchronization in esf format acc. to ntt requirements ? error checking via crc6 procedures according to itu-t g. 706 and jt g. 706 ? supports the alternate crc6 algorithm acc. to the japanese standard jt g. 706 ? alarm and performance monitoring per second 16 bit counter for crc-, framing errors, code violations, errored blocks, prbs bit errors ? insertion and extraction of alarms (ais, remote (yellow) alarm, ) ? yellow alarm generation/checking according to japanese standard jt-g.704 ? idle code insertion for selectable channels ? flexible system clock frequency different for receiver and transmitter ? supports programmable system data rates: 2.048 , 4.096, 8.192, 16.384 mbit/s and 1.544, 3.088, 6.176, 12.352 mbit/s with independent receive / transmit shifts ? mux of 4 channels into a single rail 8.192 or 6.176 mbit/s data bus and v.v. with byte - or bitinterleaved formats ? supports fractional t1 access ? elastic store for receive and transmit route clock wander and jitter compensation; controlled slip capability and slip indication; ? programmable elastic buffer size: 2 frames / 1 frame / short buffer / bypass ? provides different time-slot mapping modes ? flexible transparent modes ? programmable in-band loop code detection / generation according to tr 62411 ? channel loop back , line loop back or payload loop back capabilities (at&t tr 54016) ? pseudo random signal generator and monitor ? support for different data link schemes ? clear channel capabilities quad signaling controller ? hdlc controller bit stuffing, crc check and generation, flag generation, flag and address recognition, handling of bit oriented functions ? dl-channel protocol for esf format according to ansi t1.403 specification or according to at&t tr54016. ? robbed-bit signaling with last look capability, enhanced cas-br register access and freeze signaling indication ? provides access to serial signaling data streams
semiconductor group 184 09.98 peb 22554 general features t1 ? dl-access for f72 (slc96) format ?cas controller ? transparent mode ? fifo buffers (64 bytes deep) for efficient transfer of data packets. ? time-slot assignment any combination of time slots selectable for data transfer independent of signaling mode. useful for fractional t1 applications. mp interface ? 8/16 bit microprocessor bus interface (intel or motorola type) ? all registers directly accessible (byte or word access) ? multiplexed and non-multiplexed address bus operations ? hard / software reset options ? extended interrupt capabilities ? one second timer (internal /external access) general ? boundary scan standard ieee 1149.1 ? p-tqfp-144 package (body size 20*20) ? 3.3 v power supply ? typical power consumption 700 mw
peb 22554 general features t1 semiconductor group 185 09.98 5.1 logic symboly figure 34 quadfalc logic symbol itl10297 rclk(1-4) mclk sync sec/fsc rl1/rdip/roid(1-4) rl2/rdin/rclki(1-4) receive line interface scan boundary tms tdi tck tdo xl2/xdon/xfm(1-4) xl1/xdop/xoid(1-4) interface line transmit ddx v ssx v dd v v ss d0...15 a0...9 cs dbw ale res int microprocessor interface sclkr(1-4) rdo(1-4) rpa(1-4) rpb(1-4) rpc(1-4) receive system interface xpa(1-4) xdi(1-4) sclkx(1-4) xpc(1-4) xpb(1-4) xpd(1-4) interface system transmit im wr/rw rd/ds bhe/ble quadfalc peb 22554 tm ddr v ssr v trs rpd(1-4) (1-4) (1-4) (1-4) (1-4) (1-6) (1-6)
semiconductor group 186 09.98 peb 22554 general features t1 5.2 typical applications the figures below show multiple link applications realized with the quadfalc. figure 35 4 channel e1 interface for frame relay applications its10302 peb 22554 4 x e1/t1 quadfalc tm peb 20324 m 128x cpu mem system bus pci/generic mtsl peb 2047 munich128 memory time switch
peb 22554 general features t1 semiconductor group 187 09.98 figure 36 8 channel e1 interface to the atm layer its10303 quadfalc peb 22554 tm ram tm pxb 4220 iwe8 layer atm utopia pcm-highway 4 4 aal1 or atm-mode 4 x e1/t1 4 x e1/t1 peb 22554 quadfalc tm
semiconductor group 188 09.98 peb 22554 general features t1 6 pin descriptions t1 6.1 pin diagram figure 37 pin configuration of quadfalc p-tqfp-144 peb 22554 ddx v v ssx xl1_4/xdop4/xoid4 37 144 itp10391 xl1_1/xdop1/xoid1 xl2_4/xdon4/xfm4 tdi sec/fsc tdo im rl1_1/rdip1/roid1 rl1_4/rdip4/roid4 rl2_1/rdin1/rclki1 rl2_4/rdin4/rclki4 rclk1 ale xpa1 rclk4 xpb1 xpd1 xpd3 xpc3 xpb3 trs sclkx4 mclk sync rl2_2/rdin2/rclki2 rl2_3/rdin3/rclki3 tck int tms dbw xl1_2/xdop2/xoid2 xl1_3/xdop3/xoid3 xdi1 d15 sclkx1 rpb1 rpc1 rpd1 rdo1 rdo2 sclkr2 xdi2 xdi3 sclkx3 bhe/ble cs rd/ds sclkr3 a9 a8 a7 rdo4 a5 a3 a2 a1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 38 142 39 141 40 140 139 42 138 43 137 44 136 45 135 46 134 47 133 48 132 49 131 50 130 129 52 128 53 127 54 126 55 125 56 124 57 123 58 122 59 121 60 120 119 62 118 63 117 64 116 65 115 66 114 67 113 68 112 69 111 70 110 109 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 41 71 61 51 ss v dd v v ddr v dd v ss v ddr v dd a4 a6 v ssx d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d0 d1 d2 wr/rw rl1_3/rdip3/roid3 rl1_2/rdip2/roid2 v ddr v dd v ddr ssr v ss v ssr v v ssr v ssr xl2_3/xdon3/xfm3 xl2_2/xdon2/xfm2 xl2_1/xdon1/xfm1 v ddx ddx v v ddx ssx v v ssx n.c. rclk2 rclk3 sclkr4 sclkr1 rdo3 rpa1 rpa2 rpd2 rpc2 rpb2 rpa3 rpd3 rpc3 rpb3 rpa4 rpd4 rpc4 rpb4 sclkx2 xdi4 xpc1 xpa2 xpd2 xpc2 xpb2 xpa3 xpd4 xpc4 xpb4 xpa4 v dd v ss v ss v dd v v ss dd n.c. ss v n.c. res tm quadfalc
peb 22554 general features t1 semiconductor group 189 09.98 note: all unused input pins have to be connected to a defined level v dd or v ss . note: pu = if not connected an internal pull-up transistor ensure high input level. 6.2 pin definitions and function pin no. symbol input (i) output (o) function 83 - 74 a9 a0 i address bus address bus selects one of the internal registers for read or write. 107 -103 100 - 93 90 - 88 d15 d11 d10 d3 d2 d0 i/o data bus bi-directional three-state data lines which interface with the systems data bus. their configuration is controlled by the level of pin dbw: C 8-bit mode (dbw = 0): d0 d7 are active. d8 d15 are in high impedance and have to be connected to v dd or v ss . C 16-bit mode (dbw = 1): d0 d15 are active. in case of byte transfers, the active half of the bus is determined by a0 and bhe /ble and the selected bus interface mode (via pin im). the unused half is in high impedance. for detailed information, refer to chapter 7.2 . 62 ale i address latch enable a high on this line indicates an address on the external address/data bus. the address information provided on lines a0 a9 is internally latched with the falling edge of ale. this function allows the quadfalc to be directly connected to a multiplexed address/data bus. in this case, pins a0 a9 must be externally connected to the data bus pins.in case of demultiplexed mode this pin has to be connected directly to ground or v dd . for detailed information, refer to chapter 7.2 .
semiconductor group 190 09.98 peb 22554 general features t1 pin definitions and function (contd) pin no. symbol input (i) output (o) function 85 rd /ds i read enable (siemens/intel bus mode) this signal indicates a read operation. when the quadfalc is selected via cs the rd signal enables the bus drivers to output data from an internal register addressed via a0 a9 on to data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 7.2 . data strobe (motorola bus mode) this pin serves as input to control read/write operations. 84 wr /rw i write enable (siemens/intel bus mode) this signal indicates a write operation. when cs is active the quadfalc loads an internal register with data provided via the data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 7.2 . read/write enable (motorola bus mode) this signal distinguishes between read and write operation. 86 cs i chip select a low signal selects the quadfalc for read/write operations. 46 res i reset a low signal on this pin forces the quadfalc into reset state. during reset the quadfalc needs an active clock on pin mclk. during rese all bi-directional output stages (data bus) are in high-impedance state if signal rd is high.
peb 22554 general features t1 semiconductor group 191 09.98 87 bhe /ble i bus high enable (siemens/intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus (d8 d15). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 7.2 for detailed information. bus low enable (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus (d0 d7). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 7.2 for detailed information. 40 dbw i data bus width (bus interface mode) a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe /ble . 41 int o/od interrupt request int serves as general interrupt request which may include all interrupt sources. these interrupt sources can be masked via registers imr0 5. interrupt status is reported via registers gis (global interrupt status) and isr0 5. output characteristics (push-pull active low/high, open drain) are determined by programming the ipc register. 68 im i interface mode the level at this pin defines the bus interface mode: a low signal on this input selects the intel interface mode. a high signal on this input selects the motorola interface mode. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 192 09.98 peb 22554 general features t1 115, 138, 43, 66 rl1(1-4) rdip(1-4) roid(1-4) i i i line receiver 1 analog input from the external transformer. selected if lim1.drs = 0. receive data input positive digital input for received dual rail pcm(+) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive optical interface data unipolar data received from fibre optical interface with 1.544 mbit/s. latching of data is done with the falling edge of rclki. input sense is selected by bit rc0.rdis. the single rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 0. 116, 137, 44, 65 rl2(1-4) rdin(1-4) rclki(1-4) i i i line receiver 2 analog input from the external transformer. selected if lim1.drs = 0. receive data input negative input for received dual rail pcm(-) route signal which will be latched with the internal generated receive route clock. an internal dpll will extract the receive route clock from the incoming data pulse. the duty cycle of the receiving signal has to be closely to 50 %. the dual rail mode is selected if lim1.drs = 1 and fmr0.rc1 = 1. input sense is selected by bit rc0.rdis (after reset: active low). receive clock input receive clock input for the optical interface if lim1.drs = 1 and fmr0.rc1/0 = 00. clock frequency: 1544 khz pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 general features t1 semiconductor group 193 09.98 42, 67, 114, 132, 139 v ddr i positive power supply for the analog receiver 45, 64, 117,135, 136 v ssr i power supply ground for the analog receiver 111, 142, 39, 70 xl2(1-4) xdon(1-4) xfm(1-4) o o o transmit line 2 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output negative this digital output for transmitted dual rail pcm(-) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. transmit frame marker this digital output marks the first bit of every frame. this function is only available in the optical interface mode lim1.drs=1 and fmr0.xc1 = 0. the data will be clocked off on the positive transitions of xclk. after reset this pin is in a high impedance state until register lim1.drs is set to one. in remote loop configuration the xfm marker is not valid. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 194 09.98 peb 22554 general features t1 109, 144, 37, 72 xl1(1-4) xdop(1-4) xoid(1-4) o o o transmit line 1 analog output for the external transformer. selected if lim1.drs = 0. after reset this pin is in a high impedance state until register fmr0.xc1 is set to one. transmit data output positive this digital output for transmitted dual rail pcm(+) route signals can provide C half bauded signals with 50% duty cycle (lim0.xfb = 0) or C full bauded signals with 100% duty cycle (lim0.xfb = 1) the data will be clocked off on the positive transitions of xclk in both cases. output sense is selected by bit lim0.xdos (after reset: active low). the dual rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 1. after reset this pin is in a high impedance state until register lim1.drs is set to one. transmit optical interface data unipolar data sent to fibre optical interface with 1.544 mbit/s which will be clocked off on the positive transitions of xclk. clocking off data in nrz code is done with 100 % duty cycle. data in cmi code are shifted out with 50 % or 100 % duty cycle according to the cmi coding. output sense is selected by bit lim0.xdos (after reset: data is sent active high). the single rail mode is selected if lim1.drs = 1 and fmr0.xc1 = 0. after reset this pin is in a high impedance state until register lim1.drs is set to one. 38, 71, 110, 143 vddx i positive power supply for analog transmitter 1, 36, 73, 108 v ssx i power supply ground for analog transmitter pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 general features t1 semiconductor group 195 09.98 133 mclk i reference clock 1.544 mhz a reference clock of 1.544 mhz +/- 50 ppm must be provided to this pin. 134 nc not connected 48 sync i + pu clock synchronization if a clock is detected at the sync pin the dco-rs of the quadfalc synchronizes to this clock 1.544 mhz or 2.048 mhz (if lim1.dcoc = 1). this pin has an integrated pull up resistor. 69 sec fsc sec i +pu o o second timer input a pulse with logical one for at least two 1.544 mhz cycles will trigger the internal second timer. enabled with gpc1.fss2-0 an 8-khz frame synchronization pulse is output via this pin. the synchronization pulse is active high / low for one 1.544 / 2.048 mhz cycle (pulse width = 648 / 488 ns). second timer output activated high every second for two 1.544 mhz clock cycles. enabled with gpc1.csfp1-0. 119, 130, 47, 61 rclk(1-4) i/o+pu receive clock after reset this port is configured to an input. setting of bit pc5.crpwill switch this port to an output. input function not defined. output function: cmr1.rs1/0 = 00: receive clock extracted from the incoming data pulses. frequency: 1544 khz cmr1.rs1/0 = 01: rclk is set high in case of loss of signal (frs0.los=1). optional one of the dejittered system clocks sourced by dco-r is clocked out. clock frequency: 1544 / 6176 or 2048 / 8192 khz. selected by cmr1.rs1/0=11. wih gpc1.r1s1/0 one of the four rclk(1-4) is output on rclk1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 196 09.98 peb 22554 general features t1 8, 13, 26, 31 sclkr (1-4) i/o + pu system clock receive working clock for the receive system interface with a frequency of 16.384 / 8.192 / 4.096 / 2.048 or 12.352 /6.176 / 3.088 / 1.544 mhz. if the receive elastic store is bypassed sic1.rbs1/0 the clock supplied on this pin is ignored. if sclkr is configured to an output, the internal working clock of the receive system interface sourced by dco-r or rclk is output. in system interface multiplex mode a 16.384 / 12.352 or 8.192 / 6.176 mhz clock has to be provided on sclkr1, which is a common clock for all 4 rec. system interfaces. 9, 12, 27, 30 rdo(1-4) o receive data out received data which is sent to the system highway. clocking off data is done with the rising or falling edge (sic3.resr) of sclkr(1-4) or rclk(1-4), if the receive elastic store is bypassed. the delay between the beginning of time-slot 0 and the initial edge of sclkr(1-4) (after sypr goes active) is determined by the values of registers rc1 and rc0. if received data is shifted out with higher data, the active channel phase is defined by bits sic2.sics2-0. in system interface multiplex mode all 4 received datastreams are merged into a single datastream byte or bit interleaved on rdo1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 general features t1 semiconductor group 197 09.98 4 -7, 14 -17, 22 - 25, 32 - 35 rp(a-d)1 rp(a-d)2 rp(a-d)3 rp(a-d)4 i/o + pu i + pu o receive multifunction port a-d depending on programming of bits pc(1-4).rpc(2-0) this multifunction ports carries information to the system interface or from the system to the quadfalc. after reset these ports are configured to be inputs. with the selection of the pinfunction the in/output configuration is also achieved. depending on bit sic3.resr all outputs / inputs of the receive system interface are updated / sampled with the rising or falling edge of sclkr. synchronous pulse receive (sypr ) enabled with pc(1-4).rpc(2-0) = 000 (reset configuration). defines the beginning of time-slot 0 at system highway port rdo in conjunction with the values of registers rc0/1. in system interface multiplex mode sypr has to be provided at port rpa1 for all 4 channels and defines the beginning of time-slot 0 on port rdo1/rsig1. pulse cycle: integer multiple of 125 m s. receive frame marker (rfm) enabled with pc(1-4).rpc(2-0) = 001. cmr2.irsp = 0: the receive frame marker could be active high for a 1.544 / 2.048 mhz period during any bit position of the current frame. iprogramming is done with registers rc1/0. cmr2.irsp = 1: internal generated frame synchronization pulse generated by the dco-r circuitry. together with registers rc1/0 the frame begin on the receive system interface is defined. this frame synchronization pulse is active low 1.544 / 2.048 mhz period. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 198 09.98 peb 22554 general features t1 4 -7, 14 -17, 22 - 25, 32 - 35 rp(a-d)1 rp(a-d)2 rp(a-d)3 rp(a-d)4 o o o o o receive multiframe begin (rmfb) enabled with pc(1-4).rpc(2-0) = 010. the function depends on programming bit xc0.mfbs: mfbs = 1: rmfb marks the beginning of every received multiframe (rdo). mfbs = 0: marks the beginning of every received superframe. additional pulses every 12 frames are provided when using esf or f72 format. receive signaling marker (rsigm) enabled with pc(1-4).rpc(2-0) = 011. C marks the time-slots which are defined by register rtr1-4 of every received frame on port rdo. C when using the cas-br signaling scheme (bit xc0.brm = 1), the robbed bit of each channel every six frames is marked, if it is enabled via register xc0.brm = 1. receive signaling data (rsig) enabled with pc(1-4).rpc(2-0) = 100. the received cas signaling data is sourced by this pin. time-slots on rsig correlates directly to the time-slot assignment on rdo. in system interface multiplex mode all four received signaling datastreams are merged into a single datastream byte or bit interleaved and is transmitted on port rpb1. data link bit receive (dlr) enabled with pc(1-4).rpc(2-0) = 101. marks the dl-bit position within the data stream on rdo. freeze signaling (freeze) enabled with pc(1-4).rpc(2-0) = 110. the freeze signaling status is active high by detecting a loss of signal alarm, or a loss of frame alignment or a receive slip (pos. or neg.). it will hold high for at least one complete multiframe after the alarm disappears. setting sic2.ffs enforces a high on pin freeze. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 general features t1 semiconductor group 199 09.98 4 -7, 14 -17, 22 - 25, 32 - 35 rp(a-d)1 rp(a-d)2 rp(a-d)3 rp(a-d)4 o receive frame synchronous pulse (rfsp) enabled with pc(1-4).rpc(2-0) = 111. active low framing pulse derived from the received pcm route signal. during loss of synchronization (bit frs0.lfa), this pulse is suppressed (not influenced during alarm simulation). pulse frequency: 8 khz, pulse width: 648 ns 3, 19, 21, 50 sclkx (1-4) i/o + pu system clock transmit working clock for the transmit system interface with a frequency of 16.384 / 8.192 / 4.096 / 2.048 or 12.352 /6.176 / 3.088 / 1.544 mhz. in system interface multiplex mode a 16.384 /12.352 or 8.192 / 6.176 mhz clock has to be provided on sclkx1, which is a common clock for all 4 transmit system interfaces. 2, 18, 20, 49 xdi(1-4) i transmit data in transmit data received from the system highway. latching of data is done with rising or falling transitions of sclkx according to bit sic3.resx. the delay between the beginning of time-slot 0 and the initial edge of sclkx (after sypx goes active) is determined by the registers xc1/0. in system interface multiplex mode latching of datastream containing the 4 frames is done byte or bit interleaved on port xdi1. in higher data rates sampling of data is defined by bits sic2.sics2-0. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 200 09.98 peb 22554 general features t1 120 - 123 126 - 129 51 - 54 57 - 60 xp(a-d)1 xp(a-d)2 xp(a-d)3 xp(a-d)4 i/o + pu i + pu i + pu transmit multifunction port a-d depending on programming of bits pc(1-4).xpc(2-0) this multifunction ports carries information to the system interface or from the system to the quadfalc. after reset these ports are configured to inputs. with the selection of the pinfunction the in/output configuration is also achieved. depending on bit sic3.resx all outputs / inputs of the transmit system interface are updated / sampled with the rising or falling edge of sclkx. synchronous pulse transmit (sypx) defines the beginning of time-slot 0 at system highway port xdi in conjunction with the values of registers xc0/1. in system interface multiplex mode sypx has to be provided at port xpa1 for all 4 channels and defines the beginning of time-slot 0 on port xdi1/xsig1. enabled with pc(1-4).xpc(2-0) = 000 (reset configuration). pulse cycle: integer multiple of 125 m s. transmit multiframe synchronization (xmfs) enabled with pc(1-4).xpc(2-0) = 001 this port defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. for correct operation of xmfs no sypx pin function should be selected for the remaining multifunction ports of the same channel. in system interface multiplex mode xmfs has to be provided at port xpb1 for all 4 channels. note: a new multiframe position has been settled at least one multiframe after pulse xmfs has been supplied. pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 general features t1 semiconductor group 201 09.98 120 - 123 126 - 129 51 - 54 57 - 60 xp(a-d)1 xp(a-d)2 xp(a-d)3 xp(a-d)4 i + pu i +pu o o transmit signaling data (xsig) enabled with pc(1-4).xpc(2-0) = 010. input for transmit signaling data received from the signaling highway. optionally (sic3.ttrf) sampling of xsig data is controlled by the active high xsigm marker. in higher data rates sampling of data is defined by bits sic2.sics2-0. in system interface multiplex mode latching of the datastream containing the 4 signaling multiframes is done byte or bit interleaved on port xpc1. transmit clock (tclk) enabled with pc(1-4).xpc(2-0) = 011. a 1.544 / 6.176 mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) should not be used. optional this input functions as a clock synchronization for the dco-x circuitry with a frequency of 1.544 mhz. transmit multiframe begin (xmfb) enabled with pc(1-4).xpc(2-0) = 100. the function depends on programming bit xc0.mfbs mfbs = 1: xmfb marks the beginning of every transmitted multiframe (xdi). mfbs = 0: marks the beginning of every transmitted superframe. additional pulses every 12 frames are provided when using esf or f72 format. xmfb is active high for one 2.048 or 1.544 mbit/s period. transmit signaling marke r (xsigm) enabled with pc(1-4).xpc(2-0) = 101. C marks the transmit time-slots which are defined by register ttr1-4 of every frame transmitted via port xdi. C when using the cas-br signaling scheme, the robbed bit of each channel every six frames is marked, if it is enabled via register xc0.brm = 1. pin definitions and function (contd) pin no. symbol input (i) output (o) function
semiconductor group 202 09.98 peb 22554 general features t1 120 - 123 126 - 129 51 - 54 57 - 60 xp(a-d)1 xp(a-d)2 xp(a-d)3 xp(a-d)4 o o data link bit transmit (dlx) enabled with pc(1-4).xpc(2-0) = 110. this output provides a 4 khz signal which marks the dl-bit position within the data stream on xdi. transmit clock (xclk) enabled with pc(1-4).xpc(2-0) = 111. transmit line clock, frequency: 1.544 mhz. derived from sclkx/r, rclk or internally generated by the dco-x circuitry. 11, 29, 56, 92, 102, 125, v ss i power ground supply for digital subcircuits (0 v) for correct operation, all six pins have to be connected to ground. 10, 28, 55, 91, 101, 124, v dd i positive power supply for the digital subcircuits (3.3 v) for correct operation, all six pins have to be connected to positive power supply. 112 tdi i + pu test data input for jtag boundary scan acc. to ieee std. 1149.1 113 tdo o test data output for boundary scan 141 tms i + pu test mode select for boundary scan 140 tck i + pu test clock for boundary scan 131 trs i + pu test reset for boundary scan (active low) if the jtag boundary scan is not used this pin can be connected to pin res or vss. 63, 118 rsvd i/o + pu reserved pin definitions and function (contd) pin no. symbol input (i) output (o) function
peb 22554 general features t1 semiconductor group 203 09.98
peb 22554 functional description t1 / j1 semiconductor group 204 09.98 7 functional description t1 / j1 7.1 functional block diagram figure 38 functional block diagram peb 22554 its10300 long+short haul line interface clock/data recovery haul transmit long + short local loop line decoder alarm detector receive framer frame gen. alarm gen. line coding perform. monitor. or buffer receive elastic cas-br signaling controller cas-cc remote loop + jatt bypass bypass transmit elastic buffer or payload loop transmit backplane interface interface backplane receive controller hdlc/bom rdo(1-4) rpa(1-4) rpb(1-4) rpc(1-4) xpc(1-4) xpb(1-4) xpa(1-4) xdi(1-4) sclkx(1-4) sclkr(1-4) sec/fsc sync mclk d0...15 a0...9 falc 1 rclk(1-4) xoid(1-4) xl2/xdon/ roid(1-4) intel/motorola microprocessor interface clocking unit boundary scan jtag 1149 sclkx (1-4) receive jitter attenuator rl2/rdin/ attenuator transmit jitter rclk tdi tms tck trs tdo cs wr/rw rd/ds ale bhe/ble im dbw int tclk xpd(1-4) rl1/rdip/ rclki(1-4) xl1/xdop/ xfm(1-4) (1-4) rclk tclk (1-4) rpd(1-4) prbs monitor prbs generator line interface falc 2 falc 3 falc 4 res
peb 22554 functional description t1 / j1 semiconductor group 205 09.98 7.2 microprocessor interface the communication between the cpu and the quadfalc is done via a set of directly accessible registers. the interface may be configured as siemens/intel or motorola type with a selectable data bus width of 8 or 16 bits. the cpu transfers data to/from the quadfalc (via 64 byte deep fifos per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe /ble as shown in table 13 and 14 . in table chapter table 15 is shown how the ale (address latch enable) line is used to control the bus structure and interface type. the switching of ale allows the quadfalc to be directly connected to a multiplexed address/data bus. mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and xfifo of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. randomly mixed byte/word access to the fifos is allowed without any restrictions. table 13 data bus access (16-bit intel mode) bhe a0 register access quadfalc data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d8 C d15 1 0 register byte access (even addresses) d0 C d7 1 1 no transfer performed none
peb 22554 functional description t1 / j1 semiconductor group 206 09.98 table 14 data bus access (16-bit motorola mode) table 15 selectable bus and microprocessor interface configuration the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: n: even address complete information concerning register functions is provided in C detailed register description. ble a0 register access quadfalc data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d0 C d7 1 0 register byte access (even addresses) d8 C d15 1 1 no transfer performed none ale im microprocessor interface bus structure gnd/vdd 1 motorola demultiplexed gnd/vdd 0 intel demultiplexed switching 0 intel multiplexed siemens/intel (adr. n + 1) (adr. n) motorola (adr. n) (adr. n + 1) - - data lines d15 d8 d7 d0
peb 22554 functional description t1 / j1 semiconductor group 207 09.98 fifo structure in transmit and receive direction of the signaling controller 64-byte deep fifos for each channel are provided for the intermediate storage of data between the system internal highway and the cpu interface. the fifos are divided into two halves of 32-bytes. only one half is accessible to the cpu at any time. in case 16-bit data bus width is selected by fixing pin dbw to logical 1 word access to the fifos is enabled. data output to bus lines d0-d15 as a function of the selected interface mode is shown in figure 39 and 40 . of course, byte access is also allowed.the effective length of the accessible part of rfifo may be changed from 32 bytes (reset value) down to 2 bytes independent for each channel. figure 39 fifo word access (intel mode) 32 1 32 rfifo byte 4 byte 3 byte 2 byte 1 1 2 3 4 d15 d8 d7 d0 d0 d7 d8 d15 4 3 2 1 byte 1 byte 2 byte 3 byte 4 xfifo 32 1 32 itd01798
peb 22554 functional description t1 / j1 semiconductor group 208 09.98 figure 40 fifo word access (motorola mode) 32 1 32 rfifo byte 4 byte 3 byte 2 byte 1 1 2 3 4 d15 d8 d7 d0 d0 d7 d8 d15 4 3 2 1 byte 1 byte 2 byte 3 byte 4 xfifo 32 1 32 itd01799
peb 22554 functional description t1 / j1 semiconductor group 209 09.98 interrupt interface special events in the quadfalc are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; ipc register), which requests the cpu to read status information from the quadfalc, or to transfer data from/to quadfalc. since only one int request output is provided, the cause of an interrupt must be determined by the cpu by reading the quadfalc s interrupt status registers (cis, gis, isr0-4) that means the interrupt on pin int and the interrupt status bits are reset by reading the interrupt status registers. register isr0-4 are from type clear on read. the structure of the interrupt status registers is shown in figure 41 . figure 41 quadfalc interrupt status register structure each interrupt indication of registers isr0-4 can be selectively masked by setting the corresponding bit in the corresponding mask registers imr0-4. if the interrupt status bits are masked, they neither generate an interrupt at int nor are they visible in isr0-4. cis, the non-maskable channel interrupt status register, serves as a pointer to pending channel related global interrupt status registers. after the quadfalc has requested an interrupt by activating its int pin, the cpu should first read the channel interrupt status its10309 isr0 isr1 isr3 isr2 isr3 imr3 imr0 isr0 isr1 imr1 imr2 isr2 isr4 imr4 isr4 c1 c2 c4 c3 channel interrupt status global interrupt status (per channel) gis cis
peb 22554 functional description t1 / j1 semiconductor group 210 09.98 register cis to identify the requesting channel. the global interrupt status register serves itself as a pointer to pending interrupt status registers isr0 -4 for each channel. after reading the assigned global interrupt status register and the assigned interrupt status registers isr0- 4, the pointer in the gis and cis registers are cleared or updated if another interrupt requires service. if all pending interrupts are acknowledged by reading (cis and gis are reset), pin int goes inactive. updating of interrupt status registers isr04 , gis and cis is only prohibited during read access. masked interrupts visible in status registers the channel and global interrupt status registers indicates those interrupt status registers with active interrupt indications. an additional mode may be selected via bit gcr.vis. in this mode, masked interrupt status bits neither generate an interrupt on pin int nor are they visible in cis and gis, but are displayed in the respective interrupt status register(s) isr0..4 . this mode is useful when some interrupt status bits are to be polled in the individual interrupt status registers. notes: ? in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. ? all unmasked interrupt statuses are treated as before. please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no hierarchical polling possible), since gis only contains information on actually generated - i.e. unmasked-interrupts. 7.3 boundary scan interface identification register: 32 bit version: 1 h part number: 004d h manufacturer: 083 h in quadfalc a test access port (tap) controller is implemented. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes
peb 22554 functional description t1 / j1 semiconductor group 211 09.98 of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard: ieee 1149.1. figure 42 gives an overview. figure 42 block diagram of test access port and boundary scan test handling is performed via the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output). test data at tdi are loaded with a 4-mhz clock signal connected to tck. 1 or 0 on tms causes a transition from one controller state to an other; constant 1 on tms leads to normal operation of the chip. if no boundary scan testing is planned tms and tdi do not need to be connected since pull-up transistors ensure high input levels in this case. nevertheless it would be a good practice to put the unused inputs to defined levels. in this case, if the jtag is not used: tms = tck = 1. after switching on the device ( v dd = 0 to 3.3 v) pin trs has to reset which forces the tap controller into test logic reset state. clock generation clock reset reset tap controller -finite state machine -instruction register (3 bits) -test signal generator tck tms tdi tdo clock test control data in control bus 6 id data out ss data out bs data in identification scan (32 bits) boundary scan (n bits) 1 2 n pins itb10938 enable data out test access port trs tap controller reset
peb 22554 functional description t1 / j1 semiconductor group 212 09.98 7.4 receive path figure 43 receive clock system receive line interface for data input, three different data types are supported: ? ternary coded signals received at multifunction ports rl1 and rl2 from a -36 db ternary interface. the ternary interface is selected if lim1.drs is reset. ? digital dual rail signals received at ports rdip and rdin. the dual rail interface is selected if lim1.drs and fmr0.rc1 is set. ? unipolar data at port roid received from a fibre optical interface. the optical interface is selected if lim1.drs is set and fmr0.rc1 is reset. receive short and long haul interface the quadfalc has now an integrated short- and long- haul line interface, comprising a receive equalization network, noise filtering and programmable line build-outs (lbo). its10313 clock-data recovery dpll line decoder rdata analog- los detector alarm detector peak detector sync 1.5 mhz/ 2 mhz rl1/ 2/ rl rdip/ roid rdin/ rclki equalizer dco-r receive jitter attenuator lim1 drs . rclk(n) system fsc interface mclk clocking unit receive rclk
peb 22554 functional description t1 / j1 semiconductor group 213 09.98 receive equalization network the quadfalc automatically recovers the signals received on pins rl1/2 in a range of up to -36 db. the maximum reachable length with a 22 awg twisted-pair cable is 2000 m. after reset the quadfalc is in ?short haul mode, received signals are recovered up to -10 db of cable attenuation. switching in ?long haul mode is done by setting of register lim0.eqon. the integrated receive equalization network recovers signals with up to -36 db of cable attenuation. noise filters eliminate the higher frequency part of the received signals. the incoming data is peak detected and sliced at 55% of the peak value to produce the digital data stream. the received data is then forwarded to the clock & data recovery unit. receive line attenuation indication status register res reports the current receive line attenuation in a range from 0 to -36 db in 25 steps of approximately 1.4 db each. the least significant 5 bits of this register indicate the cable attenuation in db. these 5 bits are only valid in conjunction with the most significant two bits (res.ev1/0 = 01) . receive clock and data recovery the analog received signal at port rl1/2 is equalized and then peak-detected to produce a digital signal. the digital received signal at port rdip/n is directly forwarded to the dpll. the receive clock and data recovery extracts the route clock rclk from the data stream received at the rl1/2, rdip/rdin or roid lines and converts the data stream into a single rail, unipolar bit stream. the clock and data recovery works with the internally generated high frequency clock based on mclk. normally the clock that is output via pin rclk is the recovered clock from the signal provided by rl1/2 or rdip/n has a duty cycle close to 50 %. the free run frequency is defined by mclk = 1.544 mhz in periods with no signal. the intrinsic jitter generated in the absence of any input jitter is not more than 0.035 ui. in digital bipolar line interface mode the clock and data recovery will accept only hdb3 coded signals with 50 % duty cycle. receive line coding the b8zs line code or the ami (zcs) coding is provided for the data received from the ternary or the dual rail interface. all code violations that do not correspond to zero substitution rules will be detected. the detected errors increment the code violation counter (16 bits length). in case of the optical interface a selection between the nrz code and the cmi code (1t2b) with b8zs postprocessing is provided. if cmi code (1t2b) is selected the receive route clock will be recovered from the data stream. the 1t2b decoder does not correct any errors. in case of nrz coding data will be latched with the falling edge of pin rclki. the detected errors increment the code violation counter (16 bits length).
peb 22554 functional description t1 / j1 semiconductor group 214 09.98 when using the optical interface with nrz coding, the decoder is by-passed and no code violations will be detected. additionally, the receive line interface contains the alarm detection for alarm indication signal ais (blue alarm) and the loss of signal los (red alarm). the signal at the ternary interface is received at both ends of a transformer. figure 44 receiver configuration table 16 recommended receiver configuration values loss of signal detection there are different definitions for detecting loss of signal alarms (los) in the itu-t g.775 and at&t tr 54016. the quadfalc covers all these standards. the los indication is performed by generating an interrupt (if not masked) and activating a status bit. additionally a los status change interrupt is programmable via register gcr.sci. ? detection: an alarm will be generated if the incoming data stream has no pulses (no transitions) for a certain number (n) of consecutive pulse periods. no pulse in the digital receive interface means a logical zero on pins rdip/rdin/roid. a pulse with an amplitude less than q db below nominal is the criteria for no pulse in the analog receive interface (lim1.drs=0). the receive signal level q is programmable via three control bits lim1.ril2-0 in a range of about 900 to 50 mv differential voltage between pins rl1/2. the number n may be set via a 8 bit register pcd. the contents of the pcd register will be multiplied by 16, which results in the number of pulse periods, or better, parameter characteristic impedance 100 w ds1 r 1 ( 1 %) [ w ]100 t 2 : t 1 1 : 1 its10967 line t 2 t 1 rl2 rl1 2 r r falc
peb 22554 functional description t1 / j1 semiconductor group 215 09.98 the time which has to suspend until the alarm has to be detected. the range results therefore from 16 to 4096 pulse periods. ? recovery: in general the recovery procedure starts after detecting a logical one (digital receive interface) or a pulse (analog receive interface) with an amplitude more than q db (defined by lim1.ril2-0) of the nominal pulse. the value in the 8 bit register pcr defines the number of pulses (1 to 255) to clear the los alarm. additional recovery conditions may be programmed by register lim2. receive jitter attenuator the receive jitter attenuator is placed for each channel in the receive path. the working clock is an internally generated high frequency clock based on the clock provided on pin mclk (1.544 mhz). the jitter attenuator meets the requirements of pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and rec. i.431, g.703 and g. 824. the internal pll circuitry dco-r generates an ?jitterfree output clock which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock.the receive jitter attenuator could be either synchronized to the extracted receive clock rclk or to a 1.544 or 2.048 mhz clock provided on pin sync. the received data is written into the receive elastic buffer with rclk and are read out with the dejittered clock sourced by dco-r. the jitter attenuated clock could be output via pins rclk or sclkr. optionally a 8 khz clock is provided on pin sec/fsc. the dco-r circuitry attenuates the incoming jittered clock starting at 6 hz jitter frequency with 20 db per decade fall off. wander with a jitter frequency below 6 hz will be passed unattenuated. the intrinsic jitter in the absence of any input jitter is < 0.02ui. for some applications it might be useful starting of jitter attenuation at lower frequencies. therefore the corner frequency is switchable by the factor of ten downto 0.6 hz (lim2.scf). the dco-r circuitry is automatically centered to the nominal bit rate if the reference clock on pin sync / rclk is missed for two 2.048 or 1.544 mhz clock periods. this center function of dco-r may be optionally disabled (cmr2.dcf = 1) in order to accept a gapped reference clock. in analog line interface mode the rclk is always running. only in digital line interface mode with single rail data (nrz) a gapped clock on pin rclk may occur.
peb 22554 functional description t1 / j1 semiconductor group 216 09.98 the receive jitter attenuator works in two different modes: ? slave mode in slave mode (lim0.mas = 0) the dco1 will be synchronized to the recovered route clock. in case of los the dco-r switches automatically to master mode. if bit cmr1.dcs is set automatic switching from rclk to sync is disabled. ? master mode in master mode (lim0.mas = 1) the jitter attenuator is in free running mode if on pin sync no clock is supplied. if a clock with a frequency of 1.544 mhz (lim1.dcoc = 0) or 2.048 mhz (lim1.dcoc = 1) is applied at the sync input the dco-r will synchronize to this input. the following table shows the clock modes with the corresponding synchronization sources. mode internal los active sync input system clocks master independent fixed to vdd dco-r centered, if cmr2.dcf =0. (cmr2.dcf should not be set) master independent 1.544 or 2.048 mhz synchronized on sync input (external 1.544 or 2.048mhz) slave no fixed to vdd synchronized on line rclk1-4 , selected by cmr1.drss1/0 slave no 1.544 or 2.048 mhz synchronized on line rclk1-4 , selected by cmr1.drss1/0 slave yes fixed to vdd cmr1.dcs = 0: dco-r is centered, if cmr2.dcf = 0. (cmr2.dcf should not be set) cmr1.dcs = 1: synchronized on line rclk1-4, selected by cmr1.drss1/0 slave yes 1.544 or 2.048 mhz cmr1.dcs = 0: synchronized on sync input (external 1.544 or 2.048 mhz) cmr1.dcs = 1: synchronized on line rclk1-4, selected by cmr1.drss1/0
peb 22554 functional description t1 / j1 semiconductor group 217 09.98 the jitter attenuator meets the jitter transfer requirements of the pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and rec. i.431 and g. 703.(refer to figure 45 ). figure 45 jitter attenuation performance itd10314 1 -70 frequency attenuation -60 -50 -40 -30 -20 -10 0 10 10 100 1000 10000 100000 db hz slope slope - - 40 20 db/decade db/decade falc pub 62411_h pub 62411_l r
peb 22554 functional description t1 / j1 semiconductor group 218 09.98 jitter tolerance the quadfalc receivers tolerance to input jitter complies to itu and bellcore requirements for t1 applications. figure 46 shows the curves of different input jitter specifications stated below as well as the quadfalc performance. figure 46 jitter tolerance output jitter according to the input jitter defined by pub62411 the quadfalc generates the output jitter, which is specified in table below. specification measurement filter bandwidth output jitter (ui peak to peak) lower cutoff upper cutoff pub 62411 10 hz 8 khz < 0.015 8 khz 40 khz < 0.015 10 hz 40 khz < 0.015 broadband < 0.02 itd10308 1 0.1 jitter frequency jitter amplitude 10 100 1000 10000 100000 ui hz pub 62411 1 10 100 1000 tr-nwt 000499 cat ii ccitt g.823 itu-t i.431 falc r
peb 22554 functional description t1 / j1 semiconductor group 219 09.98 transmit jitter attenuator the transmit jitter attenuator dco-x circuitry generates a ?jitterfree transmit clock for each channel and meets the following requirements: pub 62411, pub 43802, tr-tsy 009,tr-tsy 253, tr-tsy 499 and rec. i.431 and g.703. the dco-x circuitry works internally with the same high frequency clock as the receive jitter attenuator it does. it synchronizes either to the working clock of the transmit backplane interface or the clock provided by pin tclk or the receive clock rclk (remote loop / loop-timed). the dco-x attenuates the incoming jitter starting at 6 hz with 20 db per decade fall off. with the jitter attenuated clock, which is directly dependent on the phase difference of the incoming clock and the jitter attenuated clock, data is read from the transmit elastic buffer (2 frames) or from the jatt buffer (2 frames, remote loop) wander with a jitter frequency below 6 hz are passed transparentely. the dco-x accepts gapped clocks which are used in atm or sdh/sonet applications. the jitter attenuated clock is output on pin xclk. the transmit jitter attenuator could be disabled. in that case data is read from the transmit elastic buffer with the clock sourced by pin tclk (1.544 or 6.176 mhz). synchronization between sclkx and tclk has to done externally. in the loop-timed clock configuration (lim2.elt) the dco-x circuitry generates a transmit clock which is frequency synchronized to rclk. in this configuration the transmit elastic buffer has to be enabled. figure 47 clocking in remote loop configuration its10299 equalizer dpll rl1/2 rdip/n roid drs line decoder receive jatt buffer rclk pulse shaper driver line drs xl1/2 xoid xdop/n line encoder data data transmit jitter attenuator transmit clock unit mclk rclk rclk ~ ~
peb 22554 functional description t1 / j1 semiconductor group 220 09.98 figure 48 transmit clock system note: dr = dual rail interface dco-x digital controlled oscillator transmit framer/synchronizer the following functions are performed: ? synchronization on pulse frame ? synchronization on multiframe ? error indication when synchronization is lost. in this case, ais is automatically sent to the system side and remote alarm to the remote end if en/disabled. ? initiating and controlling of resynchronization after reaching the asynchronous state. this may be automatically done by the quadfalc or user controlled via the microprocessor interface. ? detection of remote alarm (yellow alarm) indication from the incoming data stream. ? separation of service bits and data link bits. this information is stored in special status registers. ? detection of framed or unframed in band loop up/down code ? generation of various maskable interrupt statuses of the receiver functions. its10305 pulse shaper d jitter framer sclkx xl1/ xdop/ xl2/ xdon xclk a xoid dr dr elastic store xdi rclk tclk transmit attenuator dco-x sclkr internal clock of receive system tclk 4 clocking unit mclk (e1: 8mhz) interface transmit (t1: 6mhz) e1: 8mhz t1: 6mhz
peb 22554 functional description t1 / j1 semiconductor group 221 09.98 ? generation of control signals to synchronize the crc checker, and the receive elastic buffer. if programmed and applicable to the selected multiframe format, crc checking of the incoming data stream is done by generating check bits for a crc multiframe according to the crc 6 procedure (refer to itu-t rec. g.704 ). these bits are compared with those check bits that are received during the next crc multiframe. if there is at least one mismatch, the crc error counter (16 bit) will be incremented. receive elastic buffer the received bit stream is stored in the receive elastic buffer. the memory is organized as a two-frame elastic buffer with a maximum size of 2 193 bit. the size of the elastic buffer may be independently configured for the receive and transmit direction. programming of the receive buffer size is done by sic1.rbs1/0 : ? rbs1/0 = 00 : two frame buffer or 386 bits maximum of wander amplitude (peak-to-peak): (1 ui = 648 ns ) system interface clocking rate: modulo 2.048 mhz: 142 ui in channel translation mode 0 78 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: max. wander: 126 ui average delay after performing a slip: 1 frame or 193 bits ? rbs1/0 = 01 : one frame buffer or 193 bits system interface clocking rate: modulo 2.048 mhz: max. wander : 80 ui in channel translation mode 0 max. wander : 50 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: max. wander: 74 ui average delay after performing a slip: 96 bits ? rbs1/0 = 10 : short buffer or 96 bits : system interface clocking rate: modulo 2.048 mhz: max. wander : 28 ui in channel translation mode 0; channel translation mode 1 not supported system interface clocking rate: modulo 1.544 mhz: max. wander: 38 ui average delay after performing a slip: 48 bits ? rbs1/0 = 11 : bypass of the receive elastic buffer the functions are: ? clock adaption between system clock (sclkr) and internally generated route clock (rclk). ? compensation of input wander and jitter.
peb 22554 functional description t1 / j1 semiconductor group 222 09.98 ? frame alignment between system frame and receive route frame ? reporting and controlling of slips controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel, time-slot-serial data which is circularly written to the elastic buffer using internally generated receive route clock (rclk). reading of stored data is controlled by the system clock sourced by sclkr or by the receive jitter attenuator and the synchronous pulse (sypr ) in conjunction with the programmed offset values for the receive time-slot/clock-slot counters. after conversion into a serial data stream, the data is given out via port rdo. if the receive buffer is bypassed programming of the time-slot offset is disabled and data is clocked off with rclk instead of sclkr. the 24 received time-slots are translated into the 32 system time-slots in two different channel translation modes (fmr1.ctm). unequipped time-slots will be set to ff h . refer to table 17 . in one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 96 or 48 bits. in bypass mode the time-slot assigner is disabled. in this case sypr programmed as input is ignored. slips will be performed in all buffer modes except the bypass mode. after a slip is detected the read pointer is adjusted to one half of the current buffer size. the following table gives an overview of the receive buffer operating mode . figure 49 gives an idea of operation of the receive elastic buffer: a slip condition is detected when the write pointer (w) and the read pointer (r) of the memory are nearly coincident, i.e. the read pointer is within the slip limits (s +, s C). if a slip condition is detected, a negative slip (one frame or one half of the current buffer size 1) in bypass mode the clock provided on pin sclkr is ignored. clocking is done with rclk. buffer size (sic1.rbs1/0) ts offset program. (rc1/0) + sypr = input slip perform. bypass 1) disabled no short buffer not recommended, recom. sypr = output yes 1 frame not recommended, recom. sypr = output yes 2 frames enabled yes
peb 22554 functional description t1 / j1 semiconductor group 223 09.98 is skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the system interface, depending on the difference between rclk and the current working clock of the receive backplane interface. i.e. on the position of pointer r and w within the memory. a positive / negative slip is indicated in the interrupt status bits isr3.rsp and isr3.rsn. figure 49 the receive elastic buffer as circularly organized memory limits for slip detection (mode dependent) read pointer (system clock controlled) write pointer (route clock controlled) r' s+, s- r : : w: frame 2 time slots s- r frame 1 time slots moment of slip detection itd10952 w s+ slip
peb 22554 functional description t1 / j1 semiconductor group 224 09.98 table 17 channel translation modes - : ff h speech channels time-slots c. translation mode 0 c. translation mode 1 fs/dl 1 2 3 C 4 5 6 C 7 8 9 C 10 11 12 C 13 14 15 C 16 17 18 C 19 20 21 C 22 23 24 fs/dl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C C C C C C C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
peb 22554 functional description t1 / j1 semiconductor group 225 09.98 receive signaling controller each of the four signaling controller may be programmed to operate in various signaling modes. the quadfalc will perform the following signaling and data link methods: ? hdlc/sdlc or lapd access in case of common channel signaling the signaling procedure hdlc/sdlc or lapd according to q.921 will be supported. the signaling controller of the quadfalc performs the flag detection , crc checking, address comparisson and zero bit-removing. the received data flow and the address recognition features may be performed in very flexible way, to satisfy almost any practical requirements. depending on the selected address mode, the quadfalc may perform a 1 or 2 byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) and will be excluded from the address comparison. buffering of receive data is done in a 64 byte deep rfifo. refer also to chapter 8.1 . in signaling controller transparent mode, fully transparent data reception without hdlc framing is performed, i.e. without flag recognition, crc checking or bit-stuffing. this allows user specific protocol variations. the quadfalc offers the flexibility to extract data during certain time-slots. any combination of time-slots may be programmed independently for the receive and transmit direction. ? cas-bit robbing the signaling information is carried in the lsb of every sixth frame for each time-slot. the signaling controller samples the bit stream either on the receive line side or if external signaling is enabled on the receive system side via port rsig. receive signaling data is stored in the registers rs1-12. optionally the complete cas multiframe may be transmitted on pin rsig. the signaling data is clocked out with the working clock of the receive highway (sclkr) in conjunction with the rec. synchron. pulse (sypr ). data on rsig will be transmitted in the last 4 bits per time-slot and are time-slot aligned to the data on rdo. in esf format the a,b,c,d bits are placed in the bit positions 5-8 per time-slot. in f12/72 format the a and b bits are repeated in the c and d bit positions. the first 4 bits per time-slot could be optionally fixed high or low. the fs/dl time-slot is transmitted on rdo and rsig. during idle time-slots no signaling information is transmitted. data on rsig are only valid if the freeze signaling status is inactive. with fmr1.sais an all ones may be transmitted on rdo and rsig. updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss of signal, or a loss of frame alignment or a receive slip occures. the current freeze status is output
peb 22554 functional description t1 / j1 semiconductor group 226 09.98 on port freez (rpa-d) and indicated by register sis.sfs. if sis.sfs is active updating of the registers rs1-12 is disabled. optionally automatic freeze signaling may be disabled by setting bit sic3.daf. to relieve the p load from always reading the complete rs1-12 buffer every 3 msec the quadfalc notifies the p via interrupt isr0.rsc only when signaling changes from one multiframe to the next. additionally the quadfalc generates a receive signaling data change pointer (rsp1/2) which directly points to the updated rs1-12 register. . ? bit oriented messages in esf-dl channel the quadfalc supports the dl-channel protocol for esf format according to ansi t1.403 specification or according to at&t tr54016. the hdlc- and bit oriented message (bom) -receiver may be switched on/off independently. if the quadfalc is used for hdlc formats only, the bom receiver has to be switched off. if hdlc- and bom-receiver has been switched on (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. if eight or more consecutive ones are detected, the bom mode is entered. upon detection of a flag in the data stream, the quadfalc switches back to hdlc-mode. in bom-mode, the following byte format is assumed (the left most bit is received first). 111111110xxxxxx0 three different bom reception modes may be programmed (ccr1.brm+ ccr2.rbfe). if ccr2.rfbe is set, the bom-receiver will only accept bom frames after detecting 7 out of 10 equal bom pattern. buffering of receive data is done in a 64 byte deep rfifo. refer also to chapter 8.1.4 ?4 kbit/s data link access in f72 format the dl-channel protocol is supported as follows: - access is done on a multiframe basis via registers rdl1-3, - the dl bit information from frame 26 to 72 is stored in the receive fifo of the signaling controller. 7.5 system interface the quadfalc offers a flexible feature for system designers where for transmit and receive direction different system clocks and system pulses are necessary. the interface to the receive system highway is realized by two data buses, one for the data rdo and one for the signaling data rsig. the receive highway is clocked via pin sclkr, while the interface to the transmit system highway is independently clocked via pin sclkx. the frequency of these working clocks and the data rate of 2.048 / 4.096 / 8.192 / 16.384 / 1.544 / 3.088 / 6.192 / 12.352 mbit/s for the receive and transmit system interface is programmable by sic1.ssc1/0, sic2.ssc2 and sic1.ssd1, fmr1.ssd0. selectable system clock and data rates and their valid combinations are shown in the table below.
peb 22554 functional description t1 / j1 semiconductor group 227 09.98 table 18 system clocking and data rates x = valid , -- = invalid generally the data or marker on the system interface are clocked off or latched on the rising or falling edge (sic3.resr/x) of the sclkr/x clock. some clocking rates allow transmitting of time-slots in different channel- phases. each channel-phase which should be active on ports rdo, xdi, rp(a-d) and xp(a-d) is programmable by bit sic2.sics2-0, the remaining channel-phases are cleared or ignored. the signals on pin sypr in conjunction with the assigned timeslot offset in register rc0 and rc1 will define the beginning of a frame on the receive system highway.the signal on pin sypx in conjunction with the assigned timeslot offset in register xc0 and xc1 will define the beginning of a frame on the transmit system highway. adjusting the frame begin (time-slot 0, bit 0) relative to sypr/x is possible in the range of 0 - 125 sec. the minimum shift of varying the time-slot 0 begin could be programmed between 1 bit and 1/8 bit depending of the system clocking and data rate. e.g. with a clocking / data rate of 2.048 mhz shifting is done bitwise, while running the quadfalc with 16.384 mhz and 2.048 mbit/s data rate it is done by 1/8 bit. a receive frame marker rfm could be activated during any bit position of the entire frame. programming is done with registers rc1/0. the pin function rfm is selected by pc(1-4).rpc(2-0) = 001. the rfm selection disables the internal time-slot assigner, no offset programming is performed. the receive frame marker is active high for one 1.544 / 2.048 mhz cycle and is clocked off with the rising or falling edge of the clock which is in/output on port sclkr. system data rate clock rate 1.544 / 2.048 mhz clock rate 3.088 / 4.096 mhz clock rate 6.176 / 8.192 mhz clock rate 12.352 / 16.384 mhz 1.544/ 2.048 mbit/s xxxx 3.088/ 4.096 mbit/s --xxx 6.176/ 8.192 mbit/s -- -- x x 12.352 / 16.384 mbit/s -- -- -- x
peb 22554 functional description t1 / j1 semiconductor group 228 09.98 figure 50 system interface system interface multiplex mode setting this bit enables a single rail data stream of 16.384 or 8.192 or 12.352 or 6.176 mbit/s containg all four t1 frames. the receive system interface for all four channels is running with the clock provided on sclkr1 and the frame sync pulse provided on sypr1 . the transmit system interface is running with sclkx1 and sypx1 . data will be transmitted / accepted in a byte or bit interleaved format. bit interleaving is valid with the 16.384 / 8.192 / 12.352 or 6.176 mhz clocking rates. however byte interleaving is only its10298 buffer receive elastic buffer backplane receive rsigm rsig rmfb rfm dlr freez rfspq rp(a-d) syrpq dco-r rdo sclkx backplane transmit xclk xsigm xmfb dlx tclk xmfs sypxq xsig xp(a-d) signaling transmit elastic buffer transmit xdi signaling buffer receive jitter attenuator dco-r receive clock transmit jitter attenuator tclk rclk byp. plb transmit data transmit clock receive data byp. dco-r sclkr receive
peb 22554 functional description t1 / j1 semiconductor group 229 09.98 applicable with the 16.384 or 8.192 mhz clock. all four channels have to be configured equally with the following parameters: ? clocking rate : 16.384 / 8.192 / 12.352 / 6.176 mhz , sic1.ssc1/0 and sic2.ssc2 ? data rate : 16.384 / 8.192 / 12.352 / 6.176 mbit/s, sic1.ssd1, fmr1.ssd0 ? time-slot offset programming : rc1/0 , xc1/0 ? receive buffer size : sic1.rbs1/0 = 00 (2 frames) the multiplexed data stream is internal logically ored. therefore the selection of the active channel phase have to be configured different for each single channel falc. programming is done with sic2.sics2-0. in system interface multiplex mode signals on rdo2-4 and rsig2-4 are undefined, while signals on sclkr2-4, sypr 2-4, sclkx2-4, sypx 2-4, xdi2-4 and xsig2-4 are ignored.
peb 22554 functional description t1 / j1 semiconductor group 230 09.98 figure 51 receive system interface clocking itd10949 ~ ~ ~ ~ frame 1 frame 2 frame 3 frame 11 frame 12 frame 1 frame 2 ~ ~ ~ ~ bit 255 bit 0 bit 255 t 4 mbit interface 2 mbit interface programmable via rc0/1 rdo rmfb sypr sypr sclkr 8.192 mhz 1.544 mhz sclkr 2 mbit/s data rate rdo/rsig rdo/rsig (sclkr = 8.192 mhz) 4 mbit/s data rate rfm receive frame marker rsigm time-slot marker rtr1...4 4 mbit/s data rate (sclkr = 8.192 mhz) rdo/rsig bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 (sclkr = 1.544 mhz) rdo bit 192 fdl bit 1 bit 2 bit 3 bit 4 programmable via rc0/1 t dlr dl bit marker 1.544 mbit interface 1.544 mbit/s data rate 4 mbit interface 2 mbit interface (e.g. f12 frame format) sample edge edge trigger ts0 sample edge marks any bit position marks any time-slot 1) only falling trigger edge shown, depending on bit sic3.resr 1) rco/1
peb 22554 functional description t1 / j1 semiconductor group 231 09.98 figure 52 2.048 mhz receive signaling highway figure 53 1.544 mhz receive signaling highway itt10519 f01234567 d c b a abcd d c b a ts0 ts1 ts4 ts31 t sypr sclkr rdo rsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ts2 ts3 01 7 6 5 4 3 2 01 7 6 5 4 3 2012 7 6 5 4 3 fs/dl-channel idle-channel time-slot mapping acc. channel translation mode 0 f abcd itt10521 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a ts0 ts1 ts23 125 m s t sypr sclkr rdo rsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ~ ~ f f f c b ad f
peb 22554 functional description t1 / j1 semiconductor group 232 09.98 time-slot assigner the quadfalc offers the flexibility to connect data during certain time-slots, as defined by registers rtr1-4 and ttr1-4, to the rfifo and xfifo, respectively. any combinations of time-slots can be programmed for the receive and transmit directions. if ccr1.eits = 1 the selected time-slots (rtr1-4) will be stored in the rfifo of the signaling controller and the xfifo contents will be inserted into the transmit path as controlled by registers ttr1-4. table 19 time-slot assigner time-slots receive time-slot register transmit time-slot register rtr1.7 ttr1.7 0 rtr1.6 ttr1.6 1 rtr1.5 ttr1.5 2 rtr1.4 ttr1.4 3 rtr1.3 ttr1.3 4 rtr1.2 ttr1.2 5 rtr1.1 ttr1.1 6 rtr1.0 ttr1.0 7 rtr2.7 ttr2.7 8 rtr2.6 ttr2.6 9 rtr2.5 ttr2.5 10 rtr2.4 ttr2.4 11 rtr2.3 ttr2.3 12 rtr2.2 ttr2.2 13 rtr2.1 ttr2.1 14 rtr2.0 ttr2.0 15 rtr3.7 ttr3.7 16 rtr3.6 ttr3.6 17 rtr3.5 ttr3.5 18 rtr3.4 ttr3.4 19 rtr3.3 ttr3.3 20 rtr3.2 ttr3.2 21 rtr3.1 ttr3.1 22
peb 22554 functional description t1 / j1 semiconductor group 233 09.98 the format for receive fs/dl data transmission in time-slot 0 via the system interface is as shown in figure below. in order to get an undisturbed receiption even in the asynchronous state bit fmr2.dais has to be set. figure 54 receive fs/dl bits in time-slot 0 on rdo rtr3.0 ttr3.0 23 rtr4.7 ttr4.7 24 rtr4.6 ttr4.6 25 rtr4.5 ttr4.5 26 rtr4.4 ttr4.4 27 rtr4.3 ttr4.3 28 rtr4.2 ttr4.2 29 rtr4.1 ttr4.1 30 rtr4.0 ttr4.0 31 table 19 time-slot assigner (contd) time-slots receive time-slot register transmit time-slot register itd06460 12345678 fs/dl time-slot msb lsb fs/dl data bit fs/dl
peb 22554 functional description t1 / j1 semiconductor group 234 09.98 7.6 transmit path compared to the receive paths the inverse functions are performed for the transmit direction. the interface to the transmit system highway is realized by two data buses, one for the data xdi and one for the signaling data xsig. the time-slot assignment is equivalent to the receive direction. all unequipped (idle) time-slots will be ignored. latching of data is controlled by the system clock (sclkx or sclkr) and the synchronous pulse (sypx / xmfs) in conjunction with the programmed offset values for the transmit time-slot/clock-slot counters xc1/0. the frequency of the working clock 2.048 / 4.096 / 8.192 / 16.384 mhz or 1.544 / 3.088 / 6.176 / 12.352 mhz for the transmit system interface is programmable by sic1.ssc1/0 and sic2.ssc2. refer also table 18 the received bit stream on ports xdi and xsig could be multiplexed internally on a time-slot basis, if enabled by sic3.ttrf = 1. the data received at port xsig could be sampled if the transmit signaling marker xsigm is active high. data at port xdi will be sampled if xsigm is low for the respective time-slot. programming the xsigm marker is done with registers ttr1-4.
peb 22554 functional description t1 / j1 semiconductor group 235 09.98 figure 55 transmit system interface clocking: 1.544 mhz frame1 frame2 frame3 frame12 frame1 frame2 frame3 xdi xmfb xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi fdl bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 dlx dl bit marker transmit clocking t1 1.5 mhz rev.1.0 1) only falling edge mode shown 2) delay t is programmable by xc0/1; sypx t 2) xsigm time slot marker
peb 22554 functional description t1 / j1 semiconductor group 236 09.98 figure 56 transmit system interface clocking: 8.192 mhz and 4.096 mbit/s frame1 frame2 frame3 frame12 frame1 frame2 frame3 xdi xmfs sypx trigger edge 1) bit 0 sample edge 1) sclkx xdi/xsig sic2.sics2-0=000 dlx dl-bit marker sic2.sics2-0=000 transmit clocking t1 8mhz rev.1.0 1) only falling edge mode shown 2) delay t is programmable by xc0/1; sypx t 2) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 dlx dl-bit marker sic2.sics2-0=001 xdi/xsig sic2.sics2-0=001 xsigm time-slot marker xtr1...4 sic2.sics2-0=000(001)
peb 22554 functional description t1 / j1 semiconductor group 237 09.98 figure 57 2.048 mhz transmit signaling clocking figure 58 1.544 mhz transmit signaling highway itt10520 f01234567 d c b a abcd d c b a ts0 ts1 ts4 ts31 t sypx sclkx xdi xsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ts2 ts3 01 7 6 5 4 3 2 01 7 6 5 4 3 2012 7 6 5 4 3 fs/dl-channel idle-channel time-slot mapping acc. channel translation mode 0 f abcd itt10521 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a ts0 ts1 ts23 125 m s t sypr sclkr rdo rsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ~ ~ f f f c b ad f itt10522 0123456701234567 01234567 ~ ~ ~ ~ ~ ~ ~ ~ ~ d c b a abcd d c b a ts0 ts1 ts23 125 m s t sypx sclkx xdi xsig t = time-slot offset = fs/dl-bit f = signaling bits for time-slot 1-24 abcd ~ ~ f f f c b ad f ~
peb 22554 functional description t1 / j1 semiconductor group 238 09.98 figure 59 signaling marker for ccs/cas-cc applications itd06462 frame 1 frame 2 frame 3 frame 12 multiframe n (e.g. f12) 24 1 2 3 6 5 4 7 8 9 19 20 21 22 23 24 fs/ dl dl fs/ signals in channel translation mode 0 signals in channel translation mode 1 fs/ dl dl fs/ 1 18 17 16 2 1 19 20 21 22 23 24 rd0 xdi xmfb rmfb xdi rd0 xdi rd0 ~ ~ ~ ~ ~ ~~ ~ ~ ~ 1) xsigm rsigm xsigm rsigm rsigm and xsigm are programed via registers rtr1 channel 24 1) 4 to mark only ... 4 / ttr1 ... 1)
peb 22554 functional description t1 / j1 semiconductor group 239 09.98 figure 60 signaling marker for cas-br applications itd06463 frame 1 frame 2 frame 6 frame 12 multiframe n (e.g.f12) 24 1 2 3 6 5 4 7 8 9 19 20 21 22 23 24 fs/ dl dl fs/ signals in channel translation mode 0 signals in channel translation mode 1 fs/ dl dl fs/ 1 18 17 16 2 1 19 20 21 22 23 24 rd0 xdi xmfb rmfb xdi rd0 xsigm rsigm xdi rd0 xsigm rsigm signals in frames 6 and 12 of each multiframe signals in frames 6 and 12 of each multiframe rsigm and xsigm will mark the robbed bit positions if xco.brm is set high 1) ~ ~~ ~ ~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ 1) 1)
peb 22554 functional description t1 / j1 semiconductor group 240 09.98 transmit direction fs/dl data on system transmit highway (xdi), time-slot 0. figure 61 transmit fs/dl bits on xdi transmit signaling controller similar to the receive signaling controller the same signaling methods and the same time-slot assignment are provided. the quadfalc will perform the following signaling and data link methods: ? hdlc or lapd access the transmit signaling controller of the quadfalc performs the flag generation, crc generation, zero bit-stuffing and programmable idle code generation. buffering of transmit data is done in the 64 byte deep xfifo. the signaling information will be internally multiplexed with the data applied to port xdi or xsig. in signaling controller transparent mode, fully transparent data transmission without hdlc framing is performed. optionally the quadfalc supports the continuous transmission of the xfifo contents. operating in hdlc or bom mode flags or idle may be transmitted as interframe timefill. the quadfalc offers the flexibility to insert data during certain time-slots. any combinations of time-slots may be programmed separately for the receive and transmit directions. ? cas bit robbing the signaling controller inserts the bit stream either on the transmit line side or if external signaling is enabled on the transmit system side. signaling data may be sourced internally from registers xs1-12 or externally at port xsig, which is selected by register pc1-4. in external signaling mode the signaling data is sampled with the working clock of the transmit system interface (sclkx) in conjunction with the transmit synchronous pulse (sypx ). data on xsig will be latched in the bit positions 5-8 per time-slot, bits 1-4 will itd06460 12345678 fs/dl time-slot msb lsb fs/dl data bit fs/dl
peb 22554 functional description t1 / j1 semiconductor group 241 09.98 be ignored. the fs/dl bit is sampled on port xsig and inserted in the outgoing data stream. the received cas multiframe will be inserted frame aligned into the data stream on xdi. data sourced by the internal signaling controller will overwrite the external signaling data. internal multiplexing of data and signaling data may be disabled on a per time-slot basis (clear channel capability). this is also valid when using the internal and external signaling mode. ? data link access in esf and f72 format the dl-channel protocol is supported as follows: - access is done on a multiframe basis via registers xdl1-3 or - hdlc access or transparent transmission (non hdlc mode) from xfifo the signaling information stored in the xfifo will inserted in the dl bits of frame 26 to 72 in f72 format or in every other frame in esf format. transmitting may be done on a multiframe boundary. operating in hdlc or bom mode flags or idle may be transmitted as interframe timefill. transmit elastic buffer the transmit elastic store with a size of max. 2 193 bit (two -frames) serves as a temporary store for the pcm data to adapt the system clock (sclkx) to the internally generated clock for the transmit data, and to re-translate time-slot structure used in the system to that of the line side. its optimal start position is initiated when programming the transmit time-slot offset values. a difference in the effective data rates of system side and transmit side may lead to an overflow/underflow of the transmit memory: thus, errors in data transmission to the remote end may occur. this error condition (transmit slip) is reported to the microprocessor via interrupt status registers. the received bit stream from pin xdi is optionally stored in the transmit elastic buffer. the memory is organized as the receive elastic buffer. programming of the transmit buffer size is done by sic1.xbs1/0 : ? xbs1/0 = 00 : bypass of the transmit elastic buffer ? xbs1/0 = 01 : one frame buffer or 193 bits maximum of wander amplitude (peak-to-peak): (1 ui = 648 ns ) system interface clocking rate: modulo 2.048 mhz: max. wander : 80 ui in channel translation mode 0 max. wander : 50 ui in channel translation mode 1 system interface clocking rate: modulo 1.544 mhz: max. wander: 74 ui average delay after performing a slip: 96 bits ? xbs1/0 = 10 : two frame buffer or 386 bits system interface clocking rate: modulo 2.048 mhz: 142 ui in channel translation mode 0 78 ui in channel translation mode 1
peb 22554 functional description t1 / j1 semiconductor group 242 09.98 system interface clocking rate: modulo 1.544 mhz: max. wander: 126 ui average delay after performing a slip: 193 bits ? xbs1/0 = 11 : short buffer or 96 bits : system interface clocking rate: modulo 2.048 mhz: max. wander : 28 ui in channel translation mode 0; channel translation mode 1 not supported system interface clocking rate: modulo 1.544 mhz: max. wander: 38 ui average delay after performing a slip: 48 bits the functions of the transmit buffer are: ? clock adaption between system clock (sclkx/r) and internally generated transmit route clock (xclk) or externally sourced tclk. ? compensation of input wander and jitter. ? frame alignment between system frame and transmit route frame ? reporting and controlling of slips writing of received data from xdi is controlled by sclkx/r and sypx / xmfs in conjunction with the programmed offset values for the transmit time-slot/clock-slot counters. reading of stored data is controlled by the clock generated by dco-x circuitry or the externally generated tclk and the transmit framer. with the dejittered clock data is read from the transmit elastic buffer and are forwarded to the transmitter. reporting and controlling of slips is automatically done according to the receive direction. positive / negative slips are reported in interrupt status bits isr4.xsp and isr4.xsn. a re-initialization of the transmit memory is done by re-programming the transmit time-slot counter xc1 and with the next sypx pulse. after that, this memory has its optimal start position. the frequency of the working clock for the transmit system interface is programmable by sic1.ssc1/0 and sic2.ssc2 in a range of 1.544 ... 12.352 mhz / 2.048 ... 16.384 mhz. generally the data or marker on the system interface are clocked off or latched on the rising or falling edge (sic3.sps) of the sclkx clock. some clocking rates allow transmitting of time-slots / marker in different channel- phases. each channel-phase which should be latched on ports xdi and xp(a-d) is programmable by bits sic2.sics2-0 , the remaining channel-phases are cleared resp. ignored the following table gives an overview of the transmit buffer operating modes. buffer size ts offset program. slip perform. bypass enabled no
peb 22554 functional description t1 / j1 semiconductor group 243 09.98 transmitter the serial bit stream is then processed by the transmitter which has the following functions: ? frame/multiframe synthesis of one of the four selectable framing formats ? insertion of service and data link information ? ais generation (blue alarm) ? remote alarm (yellow alarm) generation ? crc generation and insertion of crc bits crc bits inversion in case of a previously received crc error or in case of activating per control bit ? generation of loop up/down code ? idle code generation per ds0 the frame / multiframe boundries of the transmitter may be externally synchronized by using the sypx / xmfs pin. any change of the transmit time-slot assignment will subsequently produce a change of the framing bit positions on the line side. this feature is required if signaling- and data link - bits are routed through the switching network and are inserted in transmit direction via the system interface. in loop-timed configuration (lim2.elt) disconnecting the control of the transmit system highway from the transmitter is done by setting fmr5.xtm. the transmitter is now in a free running mode without any possibility to actualize the multiframe position in case of changing the transmit time-slot assignment. the fs/dl bits are generated independent of the transmit system interface. for proper operation the transmit elastic buffer size should be programmed to 2 frames. the contents of selectable time-slots may be overwritten by the pattern defined via register idle. the selection of idle channels is done by programming the three-byte registers icb1 icb3. if ami coding with zero code suppression (b7-stuffing) is selected, clear channels without b7-stuffing can be defined by programming registers ccb1 ccb3. short buffer disabled yes 1 frame enabled yes 2 frames enabled yes buffer size ts offset program. slip perform.
peb 22554 functional description t1 / j1 semiconductor group 244 09.98 transmit line interface the analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the appropriate programmable shape. the unipolar data is provided by pin xdi and the digital transmitter. similar to the receive line interface three different data types are supported: figure 62 transmitter configuration table 20 recommended transmitter configuration values ? ternary signal single rail data is converted into a ternary signal which is output on pins xl1 and xl2. selection between b8zs or simple ami coding with zero code suppression (b7 stuffing) is provided. b7 stuffing may be disabled on a per time-slot basis (clear channel capability). selected by fmr0.xc1/0 and lim1.drs = 0. ? dual rail data pcm(+), pcm(-) at multifunction ports xdop and xdon with 50 % or 100 % duty cycle and with programmable polarity. line coding is done in the same way as in the ternary interface. selected by fmr0.xc1=1 and lim1.drs = 1. ? unipolar data on port xoid will be transmitted in nrz (non return to zero) with 100 % duty cycle or in cmi code with or without (sic3.cmi) preprocessed by b8zs coding to a fibre optical interface. clocking off data is done with the rising edge of the transmit clock xclk (1544 khz) and with a programmable polarity. selection is done by fmr0.xc1 = 0 and lim1.drs = 1. parameter characteristic impedance 100 w ds1 r 1 ( 1 %) [ w ]2 t2 : t1 1 : 2.4 its10968 line t 1 t 2 xl2 xl1 r 1 1 r falc r
peb 22554 functional description t1 / j1 semiconductor group 245 09.98 programmable pulse shaper and line build-out in long haul applications the transmit pulse masks are optionally generated according to fcc68 and ansi t1. 403. to reduce the crosstalk on the received signals the quadfalc offers the ability to place a transmit attenuator in the data path. transmit attenuation is selectable from 0 , -7.5, -15 or -22.5 db (register lim2.lbo2/1). ansi t1. 403 defines only 0 -15 db. the quadfalc includes a programmable pulse shaper to satisfy the requirements of ansi t1. 102 , also various ds1, dsx-1 specifications are met. the amplitude of the pulse shaper is individually programmable via the microprocessor interface to allow a maximum of different pulse templates. the line length is selected by programming the registers xpm2-0 as shown for typical values in the table below. the values with transformer ratio: 1:2.4; cable: pulp 22awg (100 w ); serial resistors: 2 w . the xpm register values are given in decimal. the transmitter requires an external step up transformer to drive the line. transmit line monitor the transmit line monitor compares the transmit line current on xl1 and xl2 with an on-chip transmit line current limiter. the monitor detects faults on the primary side of the transformer indicated by a highly increased transmit line current (more than 120 ma for at least 3 pulses) and protects the device from damage by setting the transmit line driver xl1/2 automatically in a high impedance state. two conditions will be detected by the monitor: transmit line ones density (more than 31 consecutive zeros) indicated by frs1.xlo and transmit line high currrent indicated by frs1.xls. in both cases a transmit line monitor status change interrupt will be provided. range in m xp04-xp00 xp14-xp10 xp24-xp20 xp34-xp30 decimal 0 - 35 29 27 10 3 25 - 65 29 28 10 3 55 - 95 31 28 10 2 85 - 1253127132 115 - 155 31 26 13 2 145 - 185 31 26 13 3 175 - 210 31 25 14 3
peb 22554 functional description t1 / j1 semiconductor group 246 09.98 figure 63 transmit line monitor configuration its10936 pulse shaper monitor line tri xdata xl1 xl2
peb 22554 functional description t1 / j1 semiconductor group 247 09.98 7.7 framer operating modes t1 / j1 general activated with bit fmr1.pmod = 1. pcm line bit rate : 1.544 mbit/s single frame length : 193 bit, no. 1 193 framing frequency : 8 khz organization : 24 time-slots, no. 1 24 with 8 bits each, no. 1 8 and one preceding f bit selection of one of the four permissible framing formats is performed by bits fmr4.fm1/0 . these formats are: f4 : 4-frame multiframe f12 : 12-frame multiframe (d4) esf : extended superframe f72 : 72-frame multiframe (slc96) the operating mode of the quadfalc is selected by programming the carrier data rate and characteristics, line code, multiframe structure, and signaling scheme. the quadfalc implements all of the standard and/or common framing structures pcm 24 (t1, 1.544 mbit/s) carriers. the internal hdlc-controller supports all signaling procedures including signaling frame synchronization / synthesis in all framing formats. after reset, the quadfalc must be programmed with fmr1.pmod = 1 to enable the t1(pcm24) mode. switching between the framing formats is done via bit fmr4.fm1/0 for the receiver and for the transmitter. general aspects of synchronization synchronization status is reported via bit frs0.lfa (loss of frame alignment). framing errors (pulse frame and multiframe) are counted by the framing error counter fec. asynchronous state is reached if 2 out of 4 (bit fmr4.ssc1/0 = 00), or 2 out of 5 (bit fmr4.ssc1/0 = 01), or 2 out of 6 (bit fmr4.ssc1/0 = 10), or 4 consecutive multiframe pattern in esf format are incorrect (bit fmr4.ssc1/0 = 11) . framing bits (terminal framing or multiframing) are incorrect. if auto-mode is enabled, counting of framing errors is interrupted. the resynchronization procedure may be controlled by either one of the following procedure:
peb 22554 functional description t1 / j1 semiconductor group 248 09.98 ? automatically (fmr4.auto = 1). additionally, it may be triggered by the user by setting/resetting one of the bits fmr0.frs (force resynchronization) or fmr0.exls (external loss of frame). ? user controlled, exclusively, via above control bits in the non-auto-mode (fmr4.auto = 0). addition for f12 and f72 format ft and fs bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled separately if programmed via bit fmr2.ssp. thus, a multiframe re-synchronization can be automatically initiated after detecting 2 errors out of 4/5/6 consecutive multiframing bits without influencing the state of the terminal framing. in the synchronous state, the setting of fmr0.frs or fmr0.exls resets the synchronizer and initiates a new frame search. the synchronous state is reached if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, the function of fmr0.exls is the same as above. setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. otherwise, a new frame search is started. this is useful in case the framing pattern that defines the pulseframe position is imitated periodically by a pattern in one of the speech/data channels. the control bit fmr0.exls should be used first because it starts the synchronizer to search for a definite framing candidate. to observe actions of the synchronizer, the frame search restart flag frs0.fsrf is implemented. it toggles at the start of a new frame search if no candidate has been found at previous attempt. when resynchronization is initiated, the following values apply for the time required to achieve the synchronous state in case there is one definite framing candidate within the data stream: table 21 resynchronization timing frame mode avg. max. units f4 f12 esf f72 1.0 3.5 3.4 13.0 1.5 4.5 6.125 17.75 ms
peb 22554 functional description t1 / j1 semiconductor group 249 09.98 figure 64 influences on synchronization status itd03574 auto-mode definite candidate synchronous asynchronous exls frs don doff synchronous asynchronous non-auto-mode definite candidate exls, frs don doff exls, frs synchronous multiple candidates asynchronous multiple candidates synchronous asynchronous exls, frs frs don doff exls frs 1) exls, frs frs don doff exls frs 1) : depends on the disturbance d one disturbance :
peb 22554 functional description t1 / j1 semiconductor group 250 09.98 figure 64 gives an overview of influences on synchronization status for the case of different external actions. activation of auto-mode and non-auto mode is performed via bit fmr4.auto. generally, for initiating resynchronization it is recommended to use bit: fmr0.exls first. in case where the synchronizer remains in the asynchronous state, bit fmr0.frs may be used to enforce it to lock onto the next framing candidate, although it might be a simulated one. 7.7.1 4-frame multiframe the allocation of the ft bits (bit 1 of frames 1 and 3) for frame alignment signal is shown in table 22 . the fs bit may be used for signaling. remote alarm (yellow alarm) is indicated by setting bit 2 to 0 in each time-slot. synchronization procedure for multiframe synchronization, the terminal framing bits (ft bits) are observed. the synchronous state is reached if at least one terminal framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). 7.7.2 12-frame multiframe (d4 or sf format) normally, this kind of multiframe structure only makes sense when using the cas robbed bit signaling. the multiframe alignment signal is located at the fs-bit position of every other frame (refer to table 23 ). there are two possibilities of remote alarm (yellow alarm) indication: ? bit 2 = 0 in each time-slot of a frame, selected with bit fmr0.sraf = 0 ? the last bit of the multiframe alignment signal (bit 1 of frame 12) changes from 0 to 1, selected with bit fmr0.sraf = 1. synchronization procedure in the synchronous state terminal framing (ft bits) and multiframing (fs bits) are observed, independently. further reaction on framing errors depends on the selected sync/resync procedure (via bit fmr2.ssp): table 22 4-frame multiframe structure frame number f t f s 1 2 3 4 1 C 0 C service bit service bit
peb 22554 functional description t1 / j1 semiconductor group 251 09.98 ? fmr2.ssp = 0: terminal frame and multiframe synchronization are combined. two errors within 4/5/6 framing bits (via bits fmr4.ssc1/0) of one of the above will lead to the asynchronous state for terminal framing and multiframing. additionally to the bit frs0.lfa, loss of multiframe alignment is reported via bit frs0.lmfa. the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulseframing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. ? fmr2.ssp = 1: terminal frame and multiframe synchronization are separated two errors within 4/5/6 terminal framing bits will lead to the same reaction as described above for the combined mode. two errors within 4/5/6 multiframing bits will lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported via bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. table 23 12-frame multiframe structure frame number f t f s signaling channel designation 1 2 3 4 5 6 7 8 9 10 11 12 1 C 0 C 1 C 0 C 1 C 0 C C 0 C 0 C 1 C 1 C 1 C 0 a b
peb 22554 functional description t1 / j1 semiconductor group 252 09.98 7.7.3 extended superframe ( f24, esf format) the use of the first bit of each frame for the multiframe alignment word, the data link bits, and the crc bits is shown in table 24 . synchronization procedures for multiframe synchronization the fas bits are observed. synchronous state is reached if at least one framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (fmr0.frs). in the synchronous state the framing bits (fas bits) are observed. the following conditions selected by fmr4.ssc1/0 will lead to the asynchronous state: table 24 extended superframe structure multiframe frame number f bits signaling channel designation multiframe bit number assignments fas dl crc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 193 386 579 772 965 1158 1351 1544 1737 1930 2123 2316 2509 2702 2895 3088 3231 3474 3667 3860 4053 4246 4439 C C C 0 C C C 0 C C C 1 C C C 0 C C C 1 C C C 1 m C m C m C m C m C m C m C m C m C m C m C m C C e 1 C C C e 2 C C C e 3 C C C e 4 C C C e 5 C C C e 6 C C a b c d
peb 22554 functional description t1 / j1 semiconductor group 253 09.98 ? two errors within 4/5/6 framing bits ? two or more erroneous framing bits within one esf multiframe ? more than 320 crc6 errors per second interval (fmr5.ssc2) ? 4 incorrect (1 out of 6) consecutive multiframes independent of crc6 errors. there are four multiframe synchronization modes selectable via fmr2.mcsp and fmr2.ssp. ? fmr2.mcsp/ssp = 00 : in the synchronous state, the setting of fmr0.frs or fmr0.exls resets the synchronizer and initiates a new frame search. the synchronous state will be reached again, if there is only one definite framing candidate. in the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. in asynchronous state, setting bit fmr0.frs induces the synchronizer to lock onto the next available framing candidate if there is one. at the same time the internal framing pattern memory will be cleared and other possible framing candidates are lost. ? fmr2.mcsp/ssp = 01: synchronization is achieved when 3 consecutive multiframe pattern are correctly found independent of the occurence of crc6 errors. if only one or two consecutive multiframe pattern were detected the quadfalc will stay in the asynchronous state, searching for a possible additionally available framing pattern. this procedure will be repeated until the framer has found three consecutive multiframe pattern in a row. ? fmr2.mcsp/ssp = 10: this mode has been added in order to be able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the synchronization might have been based on an alias framing pattern, setting of fmr0.frs will lead to synchronization on the next candidate available. however, only the previously assumed candidate will discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer has locked on the right pattern (no extensive crc errors). the synchronizer will be completely reset and initiates a new frame search, if there is no multiframing found. in this case bit fsr0.fsrf toggles. ? fmr2.mcsp/ssp = 11: synchronization including automatic crc6 checking synchronization is achieved when framing pattern are correctly found and the crc6 checksum is received without an error. if the crc6 check failed on the assumed framing pattern the quadfalc will stay in the asynchronous state, searching for a possible available framing pattern. this procedure will be repeated until the framer has locked on the right pattern. this automatic synchronization mode has been added in order to reduce the microprocessor load.
peb 22554 functional description t1 / j1 semiconductor group 254 09.98 remote alarm (yellow alarm) generation / detection remote alarm (yellow alarm) is indicated by the periodical pattern 1111 1111 0000 0000 in the dl bits. remote alarm will be declared even in the presence of ber 1/1000. the alarm will be reset when the yellow alarm pattern no longer is detected . depending on bit rc1.sjr the quadfalc will generate and detect the remote alarm according to jt g. 704. in the dl-bit position 16 continous ?1 are transmitted if fmr0.sraf=0 and fmr4.xra=1. crc6 generation and checking generation and checking of crc6 bits transmitted/received in the e1-e6 bit positions is done according to itu-t g.706. the crc6 checking algorithm is enabled via bit fmr1.crc. if not enabled, all check bits in the transmit direction are set to 1. in the synchronous state received crc6 errors are accumulated in a 16 bit error counter and are additionally indicated by an interrupt status. C crc6 inversion if enabled by bit rc0.crci, all crc bits of one outgoing extended multiframe are automatically inverted in case a crc error is flagged for the previous received multiframe. setting the bit rc0.xcrci will invert the crc bits before transmitted to the distant end. this function is logically ored with rc0.crci. C crc6 generation / checking according to jt g. 706 setting of rc1.sjr the quadfalc will generate and check the crc6 bits according to jt g. 706. the crc6 checksum is calculated including the fs/dl bits. in synchronous state crc6 errors will increment an error counter. 7.7.4 72-frame multiframe (slc96 ) the 72-multiframe is an alternate use of the fs-bit pattern and is used for carrying data link information. this is done by stealing some of redundant multiframing bits after the transmission of the 12-bit framing header (refer to table 25 ). the position of a and b signaling channels (robbed bit signaling) is defined by zero-to-one and one-to-zero transitions of the fs bits and is continued when the fs bits are replaced by the data link bits. remote alarm (yellow alarm) is indicated by setting bit 2 to zero in each time-slot. an additional use of the d bits for alarm indication is user defined and must be done externally.
peb 22554 functional description t1 / j1 semiconductor group 255 09.98 synchronization procedure in the synchronous state terminal framing (ft bits) and multiframing (fs bits of the framing header) are observed independently. further reaction on framing errors depends on the selected sync/resync procedure (via bit fmr2.ssp): ? fmr2.ssp = 0: terminal frame and multiframe synchronization are combined two errors within 4/5/6 framing bits (via bits fmr4.ssc1/0) of one of the above will lead to the asynchronous state for terminal framing and multiframing. additionally to the bit frs0.lfa, loss of multiframe alignment is reported via bit frs0.lmfa. the resynchronization procedure starts with synchronizing upon the terminal framing. if the pulseframing has been regained, the search for multiframe alignment is initiated. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. ? fmr2.ssp = 1: terminal frame and multiframe synchronization are separated two errors within 4/5/6 terminal framing bits will lead to the same reaction as described above for the combined mode. two errors within 4/5/6 multiframing bits will lead to the asynchronous state only for the multiframing. loss of multiframe alignment is reported via bit frs0.lmfa. the state of terminal framing is not influenced. now, the resynchronization procedure includes only the search for multiframe alignment. multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received.
peb 22554 functional description t1 / j1 semiconductor group 256 09.98 table 25 72-frame multiframe structure frame number f t f s signaling channel designation 1 2 3 4 5 6 7 8 9 10 11 12 1 C 0 C 1 C 0 C 1 C 0 C C 0 C 0 C 1 C 1 C 1 C 0 a b 13 14 15 16 17 18 19 20 21 22 23 24 1 C 0 C 1 C 0 C 1 C 0 C C 0 C 0 C 1 C 1 C 1 C d a b 25 26 27 28 66 67 68 69 70 71 72 1 C 1 C 0 C 1 C 0 C C d C d C d C d C 0 a b
peb 22554 functional description t1 / j1 semiconductor group 257 09.98 table 26 summary frame recover / out of frame conditions 1) in f12 (d4) format bit 1 in frame 12 is excluded fromthe synchronization process. format frame recover condition out of frame condition f4 only one ft pattern found, optional forcing on next available ft framing candidate 2 out of 4/5/6 incorrect ft bits f12 (d4) and f72 (slc96) fmr2.ssp = 0: combined ft + fs framing search: first searching for ft pattern with optional forcing on next available fr. candidates and then for 2 consecutive correct fs pattern 1) . fmr2.ssp = 1: separated ft + fs pattern search: loss of ft framing will start first searching for ft and then for 2 consecutive correct fs pattern 1) . loss of fs framing will start only the fs pattern 1) . search. fmr2.ssp=0 : 2 out of 4/5/6 incorrect ft or fs bits fmr2.ssp= 1 : 2 out of 4/5/6 incorrect ft bits will search ft and fs framing bits, 2 out of 4/5/6 incorrect fs bits will search only the fs framing. f24 (esf) fmr2.mcsp/ssp = 00: only one fas pattern found, optional forcing on next available fas framing candidate with discarding of all remaining fr. cand. fmr2.mcsp/ssp = 01: 3 consecutive correct multiframing found independent of crc6 errors. fmr2.mcsp/ssp = 10: choosing multiple framing pattern step by step, optional forcing on next available fas framing pattern with discarding only of the previous assumed framing candidate. fmr2.mcsp/ssp = 11: fas framing correctly found and crc6 check error free. 2 out of 4/5 incorrect fas bits or 2 out of 6 incorrect fas bits per multiframe or 4 consecutive incorrect multiframing pattern or more than 320 crc6 errors per second interval
peb 22554 functional description t1 / j1 semiconductor group 258 09.98 7.7.5 additional functions error performance monitoring and alarm handling ? alarm detection and generation alarm indication signal: detection and recovery is flagged by bit frs0.ais and isr2.ais. transmission is enabled via bit fmr1.xais. loss of signal: detection and recovery is flagged by bit frs0.los and isr2.los. remote alarm indication: detection and release is flagged by bit frs0.rra and isr2.ra/rar. transmission is enabled via bit fmr4.xra. excessive zeros: detection is flagged by bit frs1.exzd. pulse density violation: detection is flagged by bit frs1.pden and isr0.pden. transmit line shorted: detection and release is flagged by bit frs1.xls and isr1.xlsc. transmit ones density: detection and release is flagged by bit frs1.xlo and isr1.xlsc. table 27 summary of alarm detection and release alarm detection condition clear condition red alarm or loss of signal (los) no transitions (logical zeros) in a programmable time interval of 16 - 4096 consecutive pulse periods. programmable receive input signal threshold programmable number of ones (1-256) in a programmble time interval of 16 - 4096 consecutive pulse periods. a one is a signal with a level above the programmed threshold. or the pulse density is fulfilled and no more than 15 contiguous zeros during the recovery interval are detected. blue alarm or alarm indication signal (ais) fmr4.ais3 = 0: less than 3 zeros in 12 frames or 24 frames (esf), fmr4.ais3 = 1: less than 4 zeros in 12 frames or less than 6 zeros in 24 frames (esf) active for at least one multiframe. fmr4.ais3 = 0: more than 2 zeros in 12 or 24 frames (esf), fmr4.ais3 = 1: more than 3 zeros in 12 frames or more than 5 zeros in 24 frames (esf)
peb 22554 functional description t1 / j1 semiconductor group 259 09.98 rra detection operates in the presence of 10exp(-3) bit error rate. C auto modes - automatic remote alarm (yellow alarm) access if the receiver has lost its synchronization (frs0.lfa) a remote alarm (yellow alarm) could be sent automatically, if enabled by bit fmr2.axra to the distant end. in synchronous state the remote alarm bit will be removed. - automatic ais to system interface in asynchronous state the synchronizer enforces automatically an ais to the receive system interface. however, received data may be transparently switched through if bit fmr2.dais is set. - automatic clock source switching in slave mode (lim0.mas = 0) the dco-r will synchronize to the recovered route yellow alarm or remote alarm (rra) rc1.rram = 0: bit 2 = 0 in 255 consecutive time-slots or fs bit = 1 of frame12 in f12 (d4) format or 8x1,8x0 in the dl channel (esf ) rc1.rram = 1: bit 2 = 0 in every time-slot per frame or fs bit = 1 of frame12 in f12 (d4) format or 8x1,8x0 in the dl channel (esf ) rc1.rram = 0: set conditions no longer detected. rc1.rram = 1: bit 2 = 0 not detected in 3 consecutive frames or fs bit not detected in 3 consecutive mulitframes or 8x1,8x0 not detected for 3 times in a row (esf). excessive zeros (exzd) more than 7 (b8zs code) or more than 15 (ami code) contiguous zeros latched status: cleared on read pulse density violation (pden) less than 23 ones received in a floating time window of 192 bits or more than 14 consecutive zeros latched status: cleared on read transmit line short (xls) more than 32 pulse periods with highly increased transmit line current on xl1/2 no transmit line current limiter active transmit ones density (xlo) 32 consecutive zeros in the transmit data stream on xl1/2 cleared with each transmitted pulse alarm detection condition clear condition
peb 22554 functional description t1 / j1 semiconductor group 260 09.98 clock. in case of loss of signal los the dco-r switches automatically to master mode. if bit cmr1.dcs is set automatic switching from rclk to sync can be disabled. - automatic freeze signaling: updating of the received signaling information is controlled by the freeze signaling status. the freeze signaling status is automatically activated if a loss of signal, or a loss of multiframe alignment or a receive slip occures. the internal signaling buffer rs1-12 is froozen. optionally automatic freeze signaling may be disabled by setting bit sic3.daf. ? error counter the quadfalc offers six error counters each of them has a length of 16 bit. they record code violations, framing bit errors, crc6 bit errors, errored blocks and the number of received multiframes in the asynchronous state or the changes of frame alignment (cofa). counting of the multiframes in the asyn. state and the cofa parameter is done in a 6 / 2 bit counter. each of the error counter is buffered. updating the buffer is done in two modes: - one second accumulation - on demand via handshake with writing to the dec register in the one second mode an internal/external one second timer will update these buffers and reset the counter to accumulate the error events in the next one second period. the error counter can not overflow. error events occuring during reset will not lost. ? status : errored second the quadfalc supports the error performance monitoring by detecting the following alarms or error events in the received data: framing errors , crc errors , code violations , loss of frame alignment , loss of signal, alarm indication signal , receive and transmit slips. with a programmable interrupt mask register esm all these alarms or error events could generate an errored second interrupt (isr3.es) if enabled. ? second timer additionally per channel a one second timer interrupt could be internally generated to indicate that the enabled alarm status bits or the error counters have to be checked. enabled by gpc1.fss2-0 the one second timer of the selected channel may be output on port sec/fsc (gpc1.csfp1/0). optionally if all four channels of the quadfalc should synchronized to an external second timer an appropriate clock has to be provided to pin sec/fsc. selecting the external second timer is done with gcr.ses. refer also to register gpc1. clear channel capability for support of common t1 applications, clear channels can be specified via the 3-byte register bank ccb1 ccb3. in this mode the contents of selected transmit time-slots
peb 22554 functional description t1 / j1 semiconductor group 261 09.98 will not be overwritten by internal or external sourced bit robbing and zero code suppression (b7 stuffing) information. in-band loop generation and detection the quadfalc generates and detects a framed or unframed in-band loop up/actuate (00001) - and down/deactuate (001) pattern according to ansi t1. 403 with bit error rates as high as 1/100. framed or unframed in-band loop code is selected by lcr1.fllb . replacing the in-band loop codes with transmit data is done by fmr5.xld / xlu. the quadfalc also offers the ability generating and detecting of a flexible in-band loop up - and down pattern (lcr1.llbp = 1). the loop up and loop down pattern is individual programmable from 2 to 8 bit in length (lcr1.lac1/0 and lcr1.ldc1/0). programming of loop codes is done in registers lcr2 and lcr3. status and interrupt-status bits will inform the user whether loop up - or loop down code was detected. transparent mode the transparent modes are useful for loopbacks or for routing data unchanged through the quadfalc. in receive direction, transparency for ternary or dual / single rail unipolar data is always achieved if the receiver is in the synchronous state. all bits in f-bit position of the incoming multiframe are forwarded to rdo and inserted in the fs/dl time-slot or in the f-bit position. in asynchronous state the received data may be transparently switched through if bit fmr2.dais is set. setting of bit fmr2.rtm disconnects control of the elastic buffer from the receiver. the elastic buffer is now in a free running mode without any possibility to actualize the time slot assignment to a new frame position in case of re-synchronization of the receiver. together with fmr2.dais this function may be used to realize undisturbed transparent reception. setting bit fmr4.tm switches the quadfalc in transmit transparent mode: in transmit direction bit 8 of the fs/dl time-slot from the system highway (xdi) is inserted in the f-bit position of the outgoing frame. for complete transparency the internal signaling controller, idle code generation, ais alarm generation, single channel and payload loop back has to be disabled and clear channels have to be defined via registers ccb1 ? 3. pulse density detection the quadfalc examines the receive data stream on the pulse density requirement which is defined by ansi t1. 403. more than 14 consecutive zeros or less than n ones in each and every time window of 8(n+1) data bits where n=23 will be detected.
peb 22554 functional description t1 / j1 semiconductor group 262 09.98 violations of these rules are indicated by setting the status bit frs1.pden and the interrupt status bit isr0.pden. generation of the interrupt status may be programmed either with the detection or with any change of state of the pulse density alarm (gcr.sci). pseudo-random bit sequence generation and monitor the quadfalc has the added ability to generate and monitor a 2 15 -1 and 2 20 -1 pseudo- random bit sequences (prbs). the generated prbs pattern will be transmitted optionally inverted or not to the remote end via pins xl1/2 resp. xdop/n. generating and monitoring of prbs pattern is done according to itu-t o. 151 and tr62411 with maximum 14 consecutive zero restriction. the prbs monitor senses the prbs pattern in the incoming data stream. synchronization is done on the inverted and non inverted prbs pattern. the current synchronization status is reported in status and interrupt status registers. enabled by bit lcr1.eprm each prbs bit error will increment an error counter (bec). synchronization will be reached within 400 msec with a probability of 99.9% and a ber of 1/10 (pattern defined by itu-t o.151).
peb 22554 functional description t1 / j1 semiconductor group 263 09.98 payload loopback to perform an effective circuit test a line loop is implemented. if the payload loopback (fmr2.plb) is activated the received 192 bits of payload data will be looped back to the transmit direction. the framing bits, crc6 and dl bits are not looped, if fmr4.tm = 0. they are originated by the quadfalc transmitter. if the plb is enabled the transmitter and the data on pins xl1/xdop and xl2/xdon are clocked with the working clock of the receive system interface (sclkr). if fmr4.tm= 1 the received fs/dl bit is sent transparently back to the line interface. following pins are ignored: xdi, xsig, tclk, sclkx, sypx and xmfs. all the received data is processed normally. with bit fmr2.sais an ais could be sent to the system interface via pin rdo. figure 65 payload loop its09748 clock + data rec. framer elast. store trans. framer rdo xdi rclk rl1 rl2 xl1 xl2 recovery sclkx sclkr mux ais-gen elast. store
peb 22554 functional description t1 / j1 semiconductor group 264 09.98 remote loop in the remote loopback mode the clock and data recovered from the line inputs rl1/2 or rdip/rdin are routed back to the line outputs xl1/2 or xdop/xdon via the analog or digital transmitter. as in normal mode they are also processed by the synchronizer and then sent to the system interface.the remote loopback mode is selected by setting the respective control bits lim1.rl+jatt. received data may be looped with or without the transmit jitter attenuator (fifo). figure 66 remote loop its09750 rdo xdi rclk rl1 rl2 xl1 xl2 fifo xclk rclk dco1/2 framer rec. framer trans. store elast. elast. store recovery data clock + mux mux
peb 22554 functional description t1 / j1 semiconductor group 265 09.98 local loop the local loopback mode, selected by lim0.ll = 1, disconnects the receive lines rl1/2 or rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. however, the bit stream will be undisturbed transmitted on the line. however an ais to the distant end could be enabled by setting fmr1.xais without influencing the data looped back to the system interface. note that enabling the local loop will usually invoke an out of frame error until the receiver can resync to the new framing. the serial code from the transmitter and receiver has to be programmed identically. figure 67 local loop its09749 rdo xdi rclk ais-gen rl1 rl2 xl1 xl2 framer rec. framer trans. store elast. recovery data clock + mux elast. store
peb 22554 functional description t1 / j1 semiconductor group 266 09.98 single channel loop (loopback of time-slots) the channel loopback is selected via loop.eclb = 1. each of the 24 time-slots may be selected for loopback from the system pcm input (xdi) to the system pcm output (rdo). this loopback is programmed for one time-slot at a time selected by register loop. during loopback, an idle channel code programmed in register idle is transmitted to the remote end in the corresponding pcm route time-slot. for the time-slot test, sending sequences of test patterns like a 1 khz check signal should be avoided. otherwise, an increased occurrence of slips in the tested time-slot will disturb testing. these slips do not influence the other time-slots and the function of the receive memory. the usage of a quasi-static test pattern is recommended. figure 68 channel loopback its09747 rdo xdi rclk rl1 rl2 xl1 xl2 idle code framer trans. framer rec. store elast. store elast. mux mux recovery data clock +
peb 22554 functional description t1 / j1 semiconductor group 267 09.98 alarm simulation alarm simulation does not affect the normal operation of the device, i.e. all time-slots remain available for transmission. however, possible real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. the alarm simulation is initiated by setting the bit fmr0.sim. the following alarms are simulated: ? loss of signal (red alarm) ? alarm indication signal ais (blue alarm) ? loss of pulse frame ? remote alarm (yellow alarm) indication ? receive and transmit slip indication ? framing error counter ? code violation counter ? crc6 error counter some of the above indications are only simulated if the quadfalc is configured in a mode where the alarm is applicable. the alarm simulation is controlled by the value of the alarm simulation counter: frs2.esc which is incremented by setting bit: fmr0.sim. clearing of alarm indications: C automatically for los, remote (yellow) alarm, ais, and loss of synchronization and C user controlled for slips by reading the corresponding interrupt status register isr3. C error counter have to be cleared by reading the corresponding counter registers. is only possible at defined counter steps of frs2.esc. for complete simulation (frs2.esc = 0), eight simulation steps are necessary.
semiconductor group 268 09.98 peb 22554 operational description t1 / j1 8 operational description t1 / j1 8.1 signaling controller operating modes the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 4 different operating modes which can be set via the mode register. 8.1.1 hdlc mode all frames with valid addresses are forwarded directly via the rfifo to the system memory. depending on the selected address mode, the quadfalc can perform a 1 or 2 byte address recognition (mode.mds0). if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) and will be excluded from the address comparison. similarly, two compare values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the quadfalc can be called (addressed) with 6 different address combinations. hdlc frames with address fields that do not match any of the address combinations, are ignored by the falc. in case of a 1-byte address, ral1 and ral2 will be used as compare registers. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. additional information can also be read from a special register (rsis). as defined by the hdlc protocol, the quadfalc perform the zero bit insertion/deletion (bit-stuffing) in the transmit/receive data stream automatically. that means, it is guaranteed that at least after 5 consecutive 1-s a 0 will appear. non-auto-mode (mode.mds2-1=01) characteristics: address recognition, flag - and crc generation/check, bit-stuffing all frames with valid addresses are forwarded directly via the rfifo to the system memory. transparent mode 1 (mode.mds2-0=101) characteristics: address recognition, flag - and crc generation/check, bit-stuffing
semiconductor group 269 09.98 peb 22554 operational description t1 / j1 only the high byte of a 2-byte address field will be compared with registers rah1/2. the whole frame excluding the first address byte will be stored in rfifo. transparent mode 0 (mode.mds2-0=100) characteristics: flag - and crc generation/check, bit-stuffing no address recognition is performed and each frame will be stored in the rfifo. receive data flow the following figure gives an overview of the management of the received hdlc frames in the different operating modes. figure 69 receive data flow of quadfalc if ccr3 address optionally stored in rfifo crc optionally stored in rfifo if ccr3 the control field starts here! in case of on 8 bit address, ctrl stored (fifo, processed autonomously compared with (register) description of symbols: 10 register) transparent 00 note: 2) 1) mds2 10 01 mode 01 . transparent auto/8 1 0 non 1 auto/16 0 1 - non flag 2) rah1, 2 2) ral1, 2 x ral1, 2 rah1, 2) addr 2 2) "1". "1". radd . = rcrc . = rfifo 1) rsis itd06455 flag rfifo rfifo 1) rfifo i 1) rsis rsis rsis crc
semiconductor group 270 09.98 peb 22554 operational description t1 / j1 transmit data flow the frames can be transmitted as shown below. figure 70 transmit data flow of quadfalc transmitting a hdlc frame via register cmdr.xtf, the address, the control fields and the data field have to be entered in the xfifo. if ccr3.xcrc is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will be closed automatically only with a (closing) flag. the quadfalc does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 8.1.2 extended transparent mode characteristics: fully transparent in no hdlc mode, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/check, or bit-stuffing. this feature can be profitably used e.g for: ? specific protocol variations ? transmission of a bom frame ? test purposes data transmission is always performed out of the xfifo. in transparent mode, the receive data is shifted into the rfifo. control (xhf) frame hdlc transmit address flag xfifo addr ctrl flag data i checkram itd06456 crc
semiconductor group 271 09.98 peb 22554 operational description t1 / j1 8.1.3 signaling controller functions shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting bit sflg in control register ccr1. transparent transmission and reception when programmed in the extended transparent mode via the mode register (mds2-0 = 111), the quadfalc performs fully transparent data transmission and reception without hdlc framing, i.e. without ? flag insertion and deletion ? crc generation and checking ? bit-stuffing in order to enable fully transparent data transfer, bit mode.hrac has to be set. received data is always shifted into rfifo. data transmission is always performed out of xfifo by directly shifting the contents of xfifo in the outgoing datastream. transmission is initiated by setting cmdr.xtf (04 h ). a synch-byte ff h is automatically sent before the first byte of the xfifo will be transmitted. cyclic transmission (fully transparent) if the extended transparent mode is selected, the quadfalc supports the continuous transmission of the contents of the transmit fifo. after having written 1 to 32 bytes to xfifo, the command xrep.xtf via the cmdr register (bit 7 ? 0 = 00100100 = 24 h ) forces the quadfalc to transmit the data stored in xfifo repeatedly to the remote end. note: the cyclic transmission continues until a reset command (cmdr: sres) is issued or with resetting cmdr.xrep, after which continuous 1-s are transmitted. during cyclic transmission the xrep-bit has to be set with every write operation to cmdr. crc on/off features as an option in hdlc mode the internal handling of received and transmitted crc checksum can be influenced via control bits ccr3.rcrc and ccr3.xcrc. ? receive direction the received crc checksum is always assumed to be in the 2 (crc-itu) last bytes of a frame, immediately preceding a closing flag. if ccr3.rcrc is set, the received crc checksum will be written to rfifo where it precedes the frame status byte (contents of register rsis). the received crc checksum is additionally checked for
semiconductor group 272 09.98 peb 22554 operational description t1 / j1 correctness. if hdlc mode is selected, the limits for valid frame check are modified (refer to description of bit rsis.vfr). ? transmit direction if ccr3.xcrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two bytes. the transmitted frame will only be closed automatically with a (closing) flag. the quadfalc does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. 8.1.3.1 hdlc data transmission in transmit direction 2x32 byte fifo buffers are provided. after checking the xfifo status by polling the bit sis.xfw or after an interrupt isr1.xpr (transmit pool ready), up to 32 bytes may be entered by the cpu to the xfifo. the transmission of a frame can be started by issuing a xtf or xhf command via the command register. if the transmit command does not include an end of message indication (cmdr.xme), the quadfalc will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per xme command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames may be share a flag, or may be transmitted as back-to-back frames, if service of xfifo is quick enough. in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt isr1.xdu. the frame may be aborted per software cmdr.sres.
semiconductor group 273 09.98 peb 22554 operational description t1 / j1 the data transmission sequence, from the cpus point of view, is outlined in figure 71 . figure 71 interrupt driven data transmission (flow diagram) the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) is shown in figure 72 . itd08565 start transmit pool ready ? xpr interrupt, xfw bit in sis register or =1 write data (up to 32 to xfifo bytes) y message end of ? xtf/xhf command n y n command xtf/xhf end + xme itd10971 wr xfifo 32 bytes system interface interface cpu alls xpr xhf + xme 6 bytes wr xfifo xpr xpr xhf 32 bytes wr xfifo command xhf transmit frame (70 bytes) 32 32 6 r falc
semiconductor group 274 09.98 peb 22554 operational description t1 / j1 figure 72 interrupt driven transmission example 8.1.3.2 hdlc data reception also 2 32 byte fifo buffers are provided in receive direction. there are different interrupt indications concerned with the reception of data: rpf (receive pool full) interrupt, indicating that a 32-byte-block of data can be read from rfifo and the received message is not yet complete. rme (receive message end) interrupt, indicating that the reception of one message is completed. the following figure 73 gives an example of a reception sequence, assuming that a long frame (66 bytes) followed by two short frames (6 bytes each) are received. figure 73 interrupt driven reception sequence example 8.1.4 bit oriented message mode the quadfalc supports signaling and maintenance functions for t1 - primary rate interfaces using the extended super frame format. the device supports the dl-channel protocol for esf format according to t1.403-1989 ansi or to at&t tr54016 specification. the hdlc- and bit oriented message (bom) -receiver can be switched on/off independently. if the quadfalc is used for hdlc formats only, the bom receiver has to be switched off. if hdlc- and bom-receiver has been switched on itd10972 rd rfifo 32 bytes rmc receive frame 1 (66 bytes) 32 6 rpf rpf 32 2 32 bytes rd rfifo rmc rme rd status rd2 bytes rme rmc rd6 bytes rd status rmc rme rmc rd status rd6 bytes 6 rf2 rf3 falc r interface cpu interface system
semiconductor group 275 09.98 peb 22554 operational description t1 / j1 (mode.hrac/brac), an automatic switching between hdlc and bom mode is enabled. storing of received dl bit information in the rfifo of the signaling controller and transmitting the xfifo contents in the dl bit positions is enabled by ccr1.edlx/eits = 10. after reset or software-reset (cmdr.rres) the quadfalc operates in hdlc mode. if eight or more consecutive ones are detected, the bom mode is entered. upon detection of a flag in the data stream, the quadfalc switches back to hdlc-mode. operating in bom-mode, the quadfalc may receive an hdlc frame immediately, i.e. without any preceding flags. in bom-mode, the following byte format is assumed (the left most bit is received first). 111111110xxxxxx0 the quadfalc uses the ff h byte for synchronization, the next byte is stored in rfifo (first bit received: lsb) if it starts and ends with a 0. bytes starting and ending with a 1 are not stored. if there are no 8 consecutive ones detected within 32 bits, an interrupt is generated. however, byte sampling is not stopped. byte sampling in bom mode a) b) three different bom reception modes may be programmed (ccr1.brm, ccr2.rbfe). 10 byte packets: ccr1.brm = 0 after storing 10 bytes in rfifo the receive status byte marking a bom frame (rsis.hfr) is added as the eleventh byte and an interrupt (isr0.rme) is generated. the sampling of data bytes continues and interrupts are generated every 10 bytes until an hdlc flag is detected. 1111 1111 1111 0011 0100 1111 1111 0011 0100 1110 1111 0011 0100 1101 1111 sync not stored new sync 1.byte stored 1.corrupted sync 2.byte stored 2.corrupted sync corrupted sync 1111 1111 0111 0110 1101 1111 0111 0110 1111 1111 0111 0110 0111 1111 sync 1.byte stored 1.corrupted byte 2.byte stored 2.sync 3.byte stored 3.corrupted sync
semiconductor group 276 09.98 peb 22554 operational description t1 / j1 continuous reception: ccr1.brm = 1 interrupts are generated every 32 (16, 4, 2) bytes. after detecting an hdlc flag, byte sampling is stopped, the receive status byte is stored in rfifo and an rme interrupt is generated. receiption with enabled bom filter: ccr2.rbfe = 1 the bom-receiver will only accept bom frames after detecting 7 out of 10 equal bom pattern. the bom pattern is stored in the rfifo adding a receive status byte, marking a bom frame (rsis.hfr) and generating an interrupt status isr0.rme. the current state of the bom receiver is indicated in register sis.ivb. when the valid bom pattern disappears an interrupt isr0.biv is generated. the user may switch between these modes at any time. byte sampling may be stopped by deactivating the bom receiver (mode.brac). in this case the receive status byte is added, an interrupt is generated and hdlc-mode is entered. whether the quadfalc operates in hdlc or bom mode may be checked by reading the signaling status register (sis.bom). 8.1.5 4 kbit/s data link access in f72 format the quadfalc supports the dl-channel protocol using the f72 (slc96) format as follows: ? sampling of dl bits is done on a multiframe basis and stored in the registers rdl1-3. a receive multiframe begin interrupt is provided to read the received data dl bits. the contents of registers xdl1-3 is subsequently sent out on the transmit multiframe basis if it is enabled via fmr1.edl. a transmit multiframe begin interrupt requests for writing new information to the dl-bit registers. ? if enabled via ccr1.edlx/eits=10 , the dl bit information from frame 26 to 72 is stored in the receive fifo of the signaling controller.the dl bits stored in the xfifo are inserted in the outgoing datastream. if ccr1.edlx is cleared, a hdlc- or a transparent- frame could be sent or received via the rfifo / xfifo.
semiconductor group 277 09.98 peb 22554 operational description t1 / j1 8.2 operational phase the quadfalc is programmable via a microprocessor interface which enables byte or word access to all control and status registers. after reset the quadfalc has to be first initialized. general guidelines for initialization are described in section initialization. the status registers are read-only and are continuously updated. normally, the processor periodically reads the status registers to analyze the alarm status and signaling data. reset the quadfalc is forced to the reset state if a high signal is input at port res for a minimum period of 10 m s. during reset the quadfalc needs an active clock on pin mclk. all output stages are tri-stated, all internal flip-flops are reset and most of the control registers are initialized with default values. after reset bit fmr1.pmod has to be set high and the device needs up to 20 m sec to settle up to the internal clocking. after fmr1.pmod has been set the configuration shown in table 28 is initialized. table 28 configuration if initialized after reset register initiated value meaning fmr0 00 h nrz coding, no alarm simulation. fmr1 fmr2 00 h 00 h pcm 24 mode, 2.048 mbit/s system data rate, no ais transmission to remote end or system interface, payload loop off, channel translation mode 0 sic1 sic2, sic3 00 h 00 h 00 h 2.048 mhz system clocking rate, rec. buffer 2 frames, transmit buffer bypass, data sampled or transmitted on the falling edge of sclkr/x, automatic freeze signaling, data is active in the first channel phase, loop 00 h channel loop back are disabled. fmr4 fmr5 00 h 00 h remote alarm indication towards remote end disabled. lfa condition: 2 out of 4/5/6 framing bits, non-auto-synchronization mode, f12 multiframing, internal bit robbing access disabled xc0 xc1 00 h 00 h the transmit clock-slot offset is cleared. the transmit time-slot offset is cleared.
semiconductor group 278 09.98 peb 22554 operational description t1 / j1 rc0 rc1 00 h 00 h the receive clock slot offset is cleared. the receive time-slot offset is cleared. idle icb 1 ? 3 00 h 00 h idle channel code is cleared. normal operation (no idle channels selected). ccb 1 ? 300 h normal operation (no clear channel operation). lim0 lim1 pcd pcr 00 h 00 h 00 h 00 h slave mode, local loop off, analog interface selected, remote loop off pulse count for los detection cleared pulse count for los recovery cleared xpm2-0 00,03,9c h transmit pulse mask imr1-4 ff h all interrupts are disabled gcr 00 h internal second timer, power on of all 4 single falc channels, cmr1 00 h dco-r reference clock: channel 1, rclk output: dpll clock, dco-x enabled, dco-x internal reference clock cmr2 00 h sclkr selected, sclkx selected, rec. synchr. pulse sourced by sypr , tr. synchr. pulse sourced by sypx , gpc1 00 h system multiplex mode disabled, sec port input active high, fsc is sourced by channel 1, rclk1 clock source: channel 1, pc1-4 00 h , 00 h 00 h , 00 h input function of ports rp(a-d) : sypr , input function of ports xp(a-d) : sypx pc5 00 h sclkr, sclkx, rclk configured to inputs, xmfs active low rtr1-4 ttr1-4 00 h no time-slots selected mode 00 h signaling controller disabled rah1/2 ral1/2 fd h ,ff h ff h ,ff h compare register for receive address cleared table 28 configuration if initialized after reset (contd) register initiated value meaning
semiconductor group 279 09.98 peb 22554 operational description t1 / j1 initialization for a correct start up of the primary access interface a set of parameters specific to the system and hardware environment must be programmed after reset goes inactive. both the basic and the operational parameters must be programmed before the activation procedure of the pcm line starts. such procedures are specified in itu-t and dmi recommendations (e.g. fault conditions and consequent actions). setting optional parameters primarily makes sense when basic operation via the pcm line is guaranteed. table 29 gives an overview of the most important parameters in terms of signals and control bits which are to be programmed in one of the above steps. the sequence is recommended but not mandatory. accordingly, parameters for the basic and operational set up, for example, may be programmed simultaneously. the bit fmr1.pmod should always be kept high. features like channel loop back, idle channel activation, clear channel activation, extensions for signaling support, alarm simulation, ? may be activated later. transmission of alarms (e.g. ais, remote alarm) and control of synchronization in connection with consequent actions to remote end and internal system depend on the activation procedure selected. table 29 initialization parameters basic set up t1 mode select specification of line interface and clock generation line interface coding loss of signal detection/recovery conditions system clocking and data rate channel translation mode transmit offset counters receive offset counters ais to system interface fmr1.pmod = 1 lim0, lim1, xpm2-0 fmr0.xc1/0, fmr0.rc1/0 pcd, pcr, lim1, lim2 sic1.ssc1/0, sic1.ssd1, fmr1.ssd0 cmr1.irsp/irsc/ ixsp/ixsc fmr1.ctm xc0.xco, xc1.xto rc0.rco, rc1.rto fmr2.dais/sais operational set up t1 select framing framing additions synchronization mode signaling mode fmr4.fm1/0 fmr1.crc, fmr0.sraf fmr4.auto, fmr4.ssc1/0, fmr2.mcsp, fmr2.ssp fmr5.eibr, xc0.brm, mode, ccr1, ccr2, rah1/2, ral1/2
semiconductor group 280 09.98 peb 22554 operational description t1 / j1 note: read access to unused register addresses: value should be ignored. write access to unused register addresses: should be avoided, or set to 00hex. all control registers (except xfifo, xs1-12, cmdr, dec) are of type: read/write 8.3 specific t1 initialization the following is a suggestion for a basic initialization to meet most of the t1 requirements. depending on different applications and requirements any other initialization can be used. liu initialization framer initialization fmr0.xc0/1 fmr0.rc0/1 lim1.drs ccb1-3 the quadfalc supports requirements for the analog line interface as well as the digital line interface. for the analog line interface the codes ami (with and without bit 7stuffing) and b8zs are supported. for the digital line interface modes (dual or single rail) the quadfalc supports ami (with and without bit 7 stuffing) and b8zs. pcd = 0x0a los detection after 176 consecutive zeros (fulfills g.775 spec, bellcore/at&t) pcr = 0x15 los recovery after 22 ones in the pcd intervall. (fulfills g.775, bellcore/at&t) lim1.ril2-0 = 0x0 2 los threshold of 0.6 v (fulfills g.775). gcr.sci = 1 additional recovery interrupts. help to meet alarm activation and deactivation conditions in time. lim2.los2/1 = 01 automatic pulse densitiy check on 15 consecutive zeros for los recovery condition (bellcore requirement) fmr4.ssc1/0 selection of framing sync conditions fmr4.fm1/0 select framing format
semiconductor group 281 09.98 peb 22554 operational description t1 / j1 signaling controller initialization initialization of the hdlc controller: initialization of the cas-br controller after the device initialization a software reset should be executed by setting of bits cmdr.xres/rres. fmr2.axra = 1 the transmission of rai via the line interface is done automatically by the quadfalc in case of loss of frame alignment (frs0.lfa = 1). if framing has been reinstalled rai is automatically reset fmr4.auto = 1 automatic synchronization in case of definite framing candidate (frs0.fsrf). in case of multiple framing candidates and crc6 errors different resynchronization conditions can be programmed via fmr2.mcsp/ssp. mode = 0x88 hdlc receiver active, no address comparison ccr1 = 0x18 enable signaling via time-slot 0-31, interframe time fill with continous flags imr0.rme = 0 imr0.rpf = 0 imr1.xpr = 0 select interrupts for hdlc processor requests rtr4.0=1 xtr4.0 = 1 select time-slot 24 for hdlc data reception and transmission fmr5.eibr = 1 enable cas-br mode send cas-br information stored in xs1-12 imr1.case = 0 imr0.rsc = 0 enable interrupts which indicate the access to the xs1-12 cas-br registers and any data change in rs1-12
semiconductor group 282 09.98 peb 22554 operational description t1 / j1 8.4 control register description table 30 control register address arrangement address register type comment 00 100 200 300 xfifo w transmit fifo 01 101 201 301 xfifo w transmit fifo 02 102 202 302 cmdr w command register 03 103 203 303 mode r/w mode register 04 104 204 304 rah1 r/w receive address high 1 05 105 205 305 rah2 r/w receive address high 2 06 106 206 306 ral1 r/w receive address low 1 07 107 207 307 ral2 r/w receive address low 2 08 ipc r/w interrupt port configuration 09 109 209 309 ccr1 r/w common configuration register 1 0a 10a 20a 30a ccr2 r/w common configuration register 2 0c 10c 20c 30c rtr1 r/w receive timeslot register 1 0d 10d 20d 30d rtr2 r/w receive timeslot register 2 0e 10e 20e 30e rtr3 r/w receive timeslot register 3 0f 10f 20f 30f rtr4 r/w receive timeslot register 4 10 110 210 310 ttr1 r/w transmit timeslot register 1 11 111 211 311 ttr2 r/w transmit timeslot register 2 12 112 212 312 ttr3 r/w transmit timeslot register 3 13 113 213 313 ttr4 r/w transmit timeslot register 4 14 114 214 314 imr0 r/w interrupt mask register 0 15 115 215 315 imr1 r/w interrupt mask register 1 16 116 216 316 imr2 r/w interrupt mask register 2 17 117 217 317 imr3 r/w interrupt mask register 3 18 118 218 318 imr4 r/w interrupt mask register 4 1c 11c 21c 31c fmr0 r/w framer mode register 0 1d 11d 21d 31d fmr1 r/w framer mode register 1 1e 11e 21e 31e fmr2 r/w framer mode register 2 1f 11f 21f 31f loop r/w channel loop back
semiconductor group 283 09.98 peb 22554 operational description t1 / j1 20 120 220 320 fmr4 r/w framer mode register 4 21 121 221 321 fmr5 r/w framer mode register 5 22 122 222 322 xc0 r/w transmit control 0 23 123 223 323 xc1 r/w transmit control 1 24 124 224 324 rc0 r/w receive control 0 25 125 225 325 rc1 r/w receive control 1 26 126 226 326 xpm0 r/w transmit pulse mask 0 27 127 227 327 xpm1 r/w transmit pulse mask 1 28 128 228 328 xpm2 r/w transmit pulse mask 2 2b 12b 22b 32b idle r/w idle channel code 2c 12c 22c 32c xdl1 r/w transmit dl-bit register 1 2d 12d 22d 32d xdl2 r/w transmit dl-bit register 2 2e 12e 22e 32e xdl3 r/w transmit dl-bit register 3 2f 12f 22f 32f ccb1 r/w clear channel register 1 30 130 230 330 ccb2 r/w clear channel register 2 31 131 231 331 ccb3 r/w clear channel register 3 32 132 232 332 icb1 r/w idle channel register 1 33 133 233 333 icb2 r/w idle channel register 2 34 134 234 334 icb3 r/w idle channel register 3 36 136 236 336 lim0 r/w line interface mode 0 37 137 237 337 lim1 r/w line interface mode 1 38 318 238 338 pcd r/w pulse count detection 39 139 239 339 pcr r/w pulse count recovery 3a 13a 23a 33a lim2 r/w line interface register 2 3b 13b 23b 33b lcr1 r/w loop code register 1 3c 13c 23c 33c lcr2 r/w loop code register 2 3d 13d 23d 33d lcr3 r/w loop code register 3 3e 13e 23e 33e sic1 r/w system interface control 1 3f 13f 23f 33f sic2 r/w system interface control 2 table 30 control register address arrangement address register type comment
semiconductor group 284 09.98 peb 22554 operational description t1 / j1 after reset all control registers except the xfifo and xs1-12 are initialized to defined values. unused bits have to be set to logical 0. the status registers are only readable and are updated by the quadfalc. 40 140 240 340 sic3 r/w system interface control 3 44 144 244 344 cmr1 r/w clock mode register 1 45 145 245 345 cmr2 r/w clock mode register 2 46 146 246 346 gcr1 r/w global configuration register 1 47 147 247 347 esm r/w errored second mask 60 160 260 360 dec w disable error counter 70 170 270 370 xs1 w transmit signaling register 1 71 171 271 371 xs2 w transmit signaling register 2 72 172 272 372 xs3 w transmit signaling register 3 73 173 273 373 xs4 w transmit signaling register 4 74 174 274 374 xs5 w transmit signaling register 5 75 175 275 375 xs6 w transmit signaling register 6 76 176 276 376 xs7 w transmit signaling register 7 77 177 277 377 xs8 w transmit signaling register 8 78 178 278 378 xs9 w transmit signaling register 9 79 179 279 379 xs10 w transmit signaling register 10 7a 17a 27a 37a xs11 w transmit signaling register 11 7b 17b 27b 37b xs12 w transmit signaling register 12 80 180 280 380 pc1 r/w port configuration 1 81 181 281 381 pc2 r/w port configuration 2 82 182 282 382 pc3 r/w port configuration 3 83 183 283 383 pc4 r/w port configuration 4 84 184 284 384 pc5 r/w port configuration 5 85 gpc1 r/w global port configuration 1 table 30 control register address arrangement address register type comment
semiconductor group 285 09.98 peb 22554 operational description t1 / j1 transmit fifo (write) xfifo up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. writing data to xfifo can be done in 8-bit (byte) or 16-bit (word) access. the lsb is transmitted first. up to 32 bytes/16 words of transmit data can be written to the xfifo following an xpr (or alls) interrupt. command register (write) value after reset: 00 h rmc receive message complete confirmation from cpu to quadfalc that the current frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. rres receiver reset the receive line interface except the clock and data recovery unit (dpll), the receive framer, the one second timer and the receive signaling controller are reset. however the contents of the control registers will not be deleted. xrep transmission repeat if xrep is set to one together with xtf (write 24h to cmdr), the quadfalc repeatedly transmits the contents of the xfifo (1 ? 32 bytes) without hdlc framing fully transparently, i.e. without flag,crc. the cyclic transmission is stopped with an sres command or by resetting xrep. note: during cyclic transmission the xrep- bit has to be set with every write operation to cmdr. 70 xfifo xf7 xf0 (x00/x01) 70 cmdr rmc rres xrep xres xhf xtf xme sres (x02)
semiconductor group 286 09.98 peb 22554 operational description t1 / j1 xres transmitter reset the transmit framer and transmit line interface excluding the system clock generator and the pulse shaper will be reset. however the contents of the control registers will not be deleted. xhf transmit hdlc frame after having written up to 32 bytes to the xfifo, this command initiates the transmission of a hdlc frame. xtf transmit transparent frame initiates the transmission of a transparent frame without hdlc framing. xme transmit message end indicates that the data block written last to the transmit fifo completes the current frame. the quadfalc can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. sres signaling transmitter reset the transmitter of the signaling controller will be reset. xfifo is cleared of any data and an abort sequence (seven 1s) followed by interframe time fill is transmitted. in response to xres an xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission. note: the maximum time between writing to the cmdr register and the execution of the command takes 2.5 periods of the current system data rate. therefore, if the cpu operates with a very high clock rate in comparison with the quadfalc's clock, it is recommended that bit sis.cec should be checked before writing to the cmdr register to avoid any loss of commands. mode register (read/write) value after reset: 00 h 70 mode mds2 mds1 mds0 brac hrac div (x03)
semiconductor group 287 09.98 peb 22554 operational description t1 / j1 mds2-0 mode select the operating mode of the hdlc controller is selected. 000 ? reserved 001 ? reserved 010 ? 1 byte address comparison mode (ral1, 2) 011 ? 2 byte address comparison mode (rah1, 2 and ral1, 2) 100 ? no address comparison 101 ? 1 byte address comparison mode (rah1, 2) 110 ? reserved 111 ? no hdlc framing mode 1 brac bom receiver active switches the bom receiver to operational or inoperational state. 0 ? receiver inactive 1 ? receiver active hrac hdlc receiver active switches the hdlc receiver to operational or inoperational state. 0 ? receiver inactive 1 ? receiver active div data inversion setting this bit will invert the internal generated hdlc data stream. 0 ? normal operation, hdlc data stream not inverted 1 ? hdlc data stream inverted receive address byte high register 1 (read/write) value after reset: fd h in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. rah1 ? value of the first individual high address byte bit 1 (c/r-bit) is excluded from address comparison. 710 rah1 0 (x04)
semiconductor group 288 09.98 peb 22554 operational description t1 / j1 receive address byte high register 2 (read/write) value after reset: ff h rah2 value of second individual high address byte receive address byte low register 1 (read/write) value after reset: ff h ral1 value of first individual low address byte receive address byte low register 2 (read/write) value after reset: ff h ral2... value of the second individually programmable low address byte. interrupt port configuration (read/write) value after reset: 00 h unused bits have to be set to logical 0. ssyf select sync frequency only appilcable in master mode (lim0.mas = 1) and bit cmr2.dcf is cleared. 70 rah2 (x05) 70 ral1 (x06) 70 ral2 (x07) 70 ipc ssyf ic1 ic0 (08)
semiconductor group 289 09.98 peb 22554 operational description t1 / j1 0 ? reference clock at port sync is 1.544 / 2.048 mhz 1 ? reference clock at port sync is 8 khz ic0, ic1 interrupt port configuration these bits define the function of the interrupt output stage (pin int): common configuration register 1 (read/write) value after reset: 00 h brm bom receive mode (significant in bom mode only) 0 ? 10 byte packets 1 ? continuous reception edlx enable dl bit access via the transmit fifo a one in this bit position enables the internal dl- bit access via the receive / transmit fifo of the signaling controller. fmr1.edl has to be cleared switching the dl bits, stored in the xfifo transparently through the quadfalc. eits enable internal time-slot 0-31 signaling 0 internal signaling in time-slots 0-31 defined via registers rtr1-4 or ttr1-4 is disabled. 1 internal signaling in time-slots 0-31 defined via registers rtr1-4 or ttr1-4 is enabled. itf interframe time fill determines the idle (= no data to send) state of the transmit data coming from the signaling controller. 0 ? continuous logical 1 is output 1 ? continuous flag sequences are output (01111110 bit patterns) ioc1 ioc0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high 70 ccr1 brm edlx eits itf xmfa rft1 rft0 (x09)
semiconductor group 290 09.98 peb 22554 operational description t1 / j1 xmfa transmit multiframe aligned determines the synchronization between the framer and the corresponding signaling controller. 0 contents of the xfifo is transmitted without multiframe alignment. 1 contents of the xfifo is transmitted multiframe aligned. if ccr1.edlxis set, transmitting of dl bits is started in f72 format with frame 26. after receiving a complete multiframe in the time-slot mode (rtr1-4) an isr0.rme interrupt is generated, if no hdlc or bom mode is enabled. in dl bit access (ccr1.edlx/eits = 10) xmfa is not valid. note: during the transmission of the xfifo content, the sypx or xmfs interval time should not be changed, otherwise the xfifo data has to be retransmitted. rft1, rft0 rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft 1,0 can be changed dynamically C if reception is not running or C after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). note: it is seen that changing the value of rft1,0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after an rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by an rmc command (see table below ): rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes
semiconductor group 291 09.98 peb 22554 operational description t1 / j1 common configuration register 2 (read/write) value after reset: 00 h unused bits have to be set to logical 0. radd receive address pushed to rfifo if this bit is set to 1, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.mds0) is pushed to rfifo. this function is applicable in non-auto mode. rbfe receive bom filter enable setting this bit the bit oriented message (bom) -receiver will only accept bom frames after detecting 7 out of 10 equal bom pattern. the bom pattern is stored in the rfifo adding a receive status byte marking a bom frame (rsis.hfr) and an interrupt isr0.rme is generated. the current state of the bom receiver is indicated in register sis.ivb. when the valid bom pattern disappears an interrupt isr0.biv is generated. rcrc receive crc on/off only applicable in non-auto mode. if this bit is set to 1, the received crc checksum will be written to rfifo (crc-itu-t: 2 bytes). the checksum, consisting of the 2 last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsis). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for valid frame check are modified (refer to rsis.vfr ). rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc4 . ? 0 rbc3 ? 0 rbc1,0 rbc0 70 ccr2 radd rbfe rcrc xcrc (x0a)
semiconductor group 292 09.98 peb 22554 operational description t1 / j1 xcrc transmit crc on/off if this bit is set to 1, the crc checksum will not be generated internally. it has to be written as the last two bytes in the transmit fifo (xfifo). the transmitted frame will be closed automatically with a closing flag. note: the quadfalc does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. receive timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 timeslot register these bits define the received time-slots on the system highway port rdo to be extracted. additionally these registers will control the rsigm marker which can be forced high during the respective time-slots independently of bit ccr1.eits. a one in the rtr1-4 bits will sample the corresponding time-slot in the rfifo of the signaling controller, if bit ccr1.eits is set. assignments: sic2.ssc2 = 0 : ( 32 time-slots / frame ) ts0 ? time-slot 0, . . . ts31 ? time-slot 31 sic2.ssc2 = 1 : ( 24 time-slots / frame ) ts0 ? time-slot 0, . . . ts23 ? time-slot 23 0 ? the corresponding time-slot is not extracted and stored in the rfifo. 1 the contents of the selected time-slot will be stored in the rfifo. although the idle time-slots can be selected. this function will only become active, if bits ccr1.eits is set. the corresponding time-slot will be forced high on pin rsigm. 70 rtr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (x0c) rtr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (x0d) rtr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (x0e) rtr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (x0f)
semiconductor group 293 09.98 peb 22554 operational description t1 / j1 transmit timeslot register 1-4 (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ts0ts31 transmit timeslot register these bits define the transmit time-slots on the system highway to be inserted. additionally these registers will control the xsigm marker which can be forced high during the respective time-slots independently of bit ccr1.eits. a one in the ttr1-4 bits will insert the corresponding time-slot sourced by the xfifo in the data received on pin xdi, if bit ccr1.eits is set. if sic3.ttrf is set and ccr1.edlx/eits=00, insertion of data received on port xsig is controlled by this registers. assignments: sic2.ssc2 = 0 : ( 32 time-slots / frame ) ts0 ? time-slot 0, . . . ts31 ? time-slot 31 sic2.ssc2 = 1 : ( 24 time-slots / frame ) ts0 ? time-slot 0, . . . ts23 ? time-slot 23 0 ? the selected time-slot will not be inserted into the outgoing data stream. 1the contents of the selected time-slot will be inserted in the outgoing data stream from xfifo. this function will only become active, if bits ccr1.eits is set. the corresponding time-slot will be forced high on marker pin xsigm. 70 ttr1 ts0 ts1 ts2 ts3 ts4 ts5 ts6 ts7 (x10) ttr2 ts8 ts9 ts10 ts11 ts12 ts13 ts14 ts15 (x11) ttr3 ts16 ts17 ts18 ts19 ts20 ts21 ts22 ts23 (x12) ttr4 ts24 ts25 ts26 ts27 ts28 ts29 ts30 ts31 (x13)
semiconductor group 294 09.98 peb 22554 operational description t1 / j1 interrupt mask register 04 value after reset: ff h , ff h , ff h , ff h ,ff h imr0...imr4... interrupt mask register each interrupt source can generate an interrupt signal at port int (characteristics of the output stage are defined via register ipc). a 1 in a bit position of imr04 sets the mask active for the interrupt status in isr04. masked interrupt statuses neither generate a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit gcr.vis is set to 0 C be displayed in the interrupt status register if bit gcr.vis is set to 1. after reset, all interrupts are dis abled. 70 imr0 rme rfs isf rmb rsc crc6 pden rpf (x14) imr1 case rdo alls xdu xmb xlsc xpr (x15) imr2 far lfa mfar lmfa ais los rar ra (x16) imr3 es sec llbsc rsn rsp (x17) imr4 xsp xsn (x18)
semiconductor group 295 09.98 peb 22554 operational description t1 / j1 framer mode register 0 (read/write) value after reset: 00 h xc1xc0 transmit code serial code transmitter is independent to the receiver. 00 nrz (optical interface) 01 cmi (1t2b + b8zs), (optical interface) 10 ami coding with zero code suppression (zcs, b7 - stuffing). disabling of the zcs is done by activating the clear channel mode via register ccb1-3. (ternary or digital interface) 11 b8zs code (ternary or digital dual rail interface) rc1rc0 receive code serial code receiver is independent to the transmitter. 00 nrz (optical interface) 01 cmi (1t2b + b8zs), (optical interface) 10 ami coding with zero code suppression (zcs, b7 - stuffing), (ternary or digital dual rail interface) 11 b8zs code (ternary or digital dual rail interface) frs force resynchronization a transition from low to high will force the frame aligner to execute a resynchronization of the pulse frame. in the asynchronous state, a new frame position is assumed at the next candidate if there is one. otherwise, a new frame search with the meaning of a general reset is started. in the synchronous state this bit will have the same meaning as bit fmr0.exls except if fmr2.mcsp=1. sraf select remote (yellow) alarm format for f12 and esf format 0 f12: bit2 = 0 in every channel. esf: pattern 1111 1111 0000 0000 in data link channel. 1 f12: fs bit of frame 12. esf: bit2 = 0 in every channel exls external loss of frame with a low to high transition a new frame search will be started. this has the meaning of a general reset of the internal frame alignment unit. synchronous state is reached only if there is one definite framing candidate. in the case of multiple candidates, the setting of the bit 70 fmr0 xc1 xc0 rc1 rc0 frs sraf exls sim (x1c)
semiconductor group 296 09.98 peb 22554 operational description t1 / j1 fmr0.frs forces the receiver to lock onto the next available framing position. sim alarm simulation setting/resetting this bit initiates internal error simulation of: ais (blue alarm), loss of signal (red alarm), loss of frame alignment, remote (yellow) alarm, slip, framing errors, crc errors, code violations. the error counters fec, cvc, cec, ebc will be incremented. the selection of simulated alarms is done via the error simulation counter: frs2.esc2-0 which will be incremented with each setting of bit fmr0.sim. for complete checking of the alarm indications eight simulation steps are necessary (frs2.esc2-0 = 0 after a complete simulation). framer mode register 1 (read/write) value after reset: 00 h ctm channel translation mode 0 channel translation mode 0 1 channel translation mode 1 edl enable dl-bit access via register xdl1-3 only applicable in f4, f24 or f72 frame format. 0 normal operation. the dl-bits will be taken from system highway or if enabled via ccr1.edlx from the xfifo of the signaling controller. 1 dl-bit register access. the dl-bit information will be taken from the registers xdl1-3 and will overwrite the dl-bits received at the system highway (pin xdi) or the internal xfifo of the signaling controller. however, transmitting contents of registers xdl1-3 will be disabled if transparent mode is enabled (fmr4.tm). pmod pcm mode for t1 application this bit must be set high. switching into t1 mode the device needs up to 10 m sec to settle up to the internal clocking. fmr1.pmod of all 4 channels has to be set equally. 70 fmr1 ctm edl pmod crc ecm ssd0 xais (x1d)
semiconductor group 297 09.98 peb 22554 operational description t1 / j1 0 pcm 30 or e1 mode. 1 pcm 24 or t1 mode. crc enable crc6 this bit is only significant when using the esf format. 0 ? crc6 check/generation disabled. for transmit direction, all crc bit positions are set to 1. 1 ? crc6 check/generation enabled. ecm error counter mode the function of the error counters (fec,cec,cvc,ebc) will be determined by this bit. 0 ? before reading an error counter the corresponding bit in the disable error counter register (dec) has to be set. in 8 bit access the low byte of the error counter should always be read before the high byte. the error counters will be reset with the rising edge of the corresponding bits in the dec register. 1 every second the error counter will be latched and then automatically be reset. the latched error counter state should be read within the next second. reading the error counter during updating should be avoided. ssd0 select system date rate 0 sic1.ssd1, fmr1.ssd0 and sic2.ssc2 define the data rate on the system highway. programming ssd1/ssd0 and corresponding data rate is shown below. sic2.ssc2 = 0: 002.048 mbit/s 014.096 mbit/s 108.192 mbit/s 1116.384 mbit/s sic2.ssc2 = 1: 001.544 mbit/s 013.088 mbit/s 106.176 mbit/s 1112.352 mbit/s
semiconductor group 298 09.98 peb 22554 operational description t1 / j1 xais transmit ais towards remote end sends ais (blue alarm) via ports: xl1, xl2 towards the remote end. if local loop mode is enabled the transmitted data is looped back to the system internal highway without any changes. framer mode register 2 (read/write) value after reset: 00 h mcsp multiple candidates synchronization procedure ssp select sync/resync procedure together with bit fmr2.ssp the synchronization mode of the receive framer is defined: mcsp/ssp: 00 f12/72 format: specified number of errors in both ft framing and fs framing lead to loss of sync (frs0.lfa is set). in the case of fs bit framing errors, bit frs0.lmfa is set additionally. a complete new synchronization procedure is initiated to regain pulseframe alignment and then multiframe alignment. f24: normal operation: synchronization is achieved only on verification the framing pattern. 01 f12/72: specified number of errors in ft framing has the same effect as above. specified number of errors in fs framing only initiates a new search for multiframe alignment without influencing pulseframe synchronous state (frs0.lmfa is set). f24: synchronous state is reached when three consecutive multiframe pattern are correctly found independent of the occurence of crc6 errors. 10 a one will enable a synchronization mode which is able to choose multiple framing pattern candidates step by step. i.e. if in synchronous state the crc error counter indicates that the 70 fmr2 mcsp ssp dais sais plb axra exze (x1e)
semiconductor group 299 09.98 peb 22554 operational description t1 / j1 synchronization might have been based on an alias framing pattern, setting of fmr0.frs will lead to synchronization on the next candidate available. however, only the previously assumed candidate will be discarded in the internal framing pattern memory. the latter procedure can be repeated until the framer has locked on the right pattern (no extensive crc errors). therefor bit fmr1.crc must be set. 11 f24: synchronization is achieved on verification the framing pattern and the crc6 bits. synchronous state is reached when framing pattern and crc6 checksum are correctly found. for correct operation the crc check must be enabled by setting bit fmr1.crc6. dais disable ais to system interface 0 ais is automatically inserted into the data stream to rdo if quadfalc is in asynchronous state. 1 automatic ais insertion is disabled. furthermore, ais insertion can be initiated by programming bit fmr2.sais. sais send ais towards system interface sends ais (blue alarm) via output rdo towards system interface. this function is not influenced by bit fmr2.dais. plb payload loop back 0 ? normal operation. payload loop is disabled. 1 the payload loopback will loop the data stream from the receiver section back to transmitter section. looped data is output on pin rdo. data received at port xdi, xsig, sypx and xmfs will be ignored. with fmr4.tm=1 all 193 bits per frame will be looped back. if fmr4.tm=0 the dl- or fs- or crc- bits will be generated internally. ais is sent immediately on port rdo by setting the fmr2.sais bit. during payload loop is active the receive time-slot offset (registers rc1/0) should not be changed. a write access to register xc1 will set the read/write pointer of the transmit elastic buffer into its optimal position to ensure a maximum wander compensation. axra automatic transmit remote alarm 0 ? normal operation 1 the remote alarm (yellow alarm) bit will be automatically set in the outgoing data stream if the receiver is in asynchronous
semiconductor group 300 09.98 peb 22554 operational description t1 / j1 state (frs0.lfa bit is set). in synchronous state the remote alarm bit will be reset. exze excessive zeros detection enable selects error detection mode in the bipolar receive bit stream. 0 only bipolar violations are detected. 1 bipolar violations and zero strings of 8 or more contiguous zeros in b8zs code or more than 15 contiguous zeros in ami code are detected additionally and counted in the code violation counter cvc. loop (read/write) value after reset: 00 h rtm receive transparent mode setting this bit disconnects control of the internal elastic store from the receiver. the elastic store is now in a free running mode without any possibility to actualize the time slot assignment to a new frame position in case of re-synchronization of the receiver. this function can be used in conjunction with the disable ais to system interface feature (fmr2.dais) to realize undisturbed transparent reception. this bit should be enabled in case of unframed data reception mode. eclb enable channel loop back 0 disables the channel loop back. 1 enables the channel loop back selected by this register. cla4cla0 channel address for loop back cla = 124 selects the channel. during loop back, the contents of the associated outgoing channel at ports xl1/xdop/xoid and xl2/xdon is equal to the idle channel code programmed in register idle. 70 loop rtm eclb cla4 cla0 (x1f)
semiconductor group 301 09.98 peb 22554 operational description t1 / j1 framer mode register 4 (read/write) value after reset: 00 h ais3 select ais condition 0 ais (blue alarm) is indicated (frs0.ais) when two or less zeros in the received bit stream are detected in a time interval of 12 frames (f4, f12, f72) or 24 frames (esf). 1 ais (blue alarm) detection is only enabled when quadfalc is in asynchronous state. the alarm is indicated (frs0.ais) when C three or less zeros within a time interval of 12 frames (f4, f12, f72), or C five or less zeros within a time interval of 24 frames (esf) are detected in the received bit stream. tm transparent mode setting this bit enables the transparent mode: in transmit direction bit 8 of every fs/dl time-slot from the system internal highway (xdi) is inserted in the f-bit position of the outgoing frame. internal framing generation, insertion of crc and dl data is disabled. xra transmit remote alarm (yellow alarm) if high, remote alarm is sent via pcm route. clearing the bit will remove the remote alarm pattern. remote alarm indication depends on the multiframe structure as follows: f4: bit2 = 0 in every speech channel f12: C fmr0.sraf = 0: bit2 = 0 in every speech channel C fmr0.sraf = 1: fs-bit of frame 12 is forced to 1 esf: C fmr0.sraf = 0: pattern 1111111100000000 11111111000 in data link channel C fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel ssc1/0 select sync conditions loss of frame alignment (frs0.lfa or opt. frs0.lmfa) is declared if 00 = 2 out of 4 framing bits 70 fmr4 ais3 tm xra ssc1 ssc0 auto fm1 fm0 (x20)
semiconductor group 302 09.98 peb 22554 operational description t1 / j1 01 = 2 out of 5 framing bits 10 = 2 out of 6 framing bits in f4/12/72 format 10 = 2 out of 6 framing bits per multiframe period in esf format 11 = 4 consecutive multiframe pattern in esf format are incorrect. are incorrect. it depends on the selected multiframe format and optionally on bit fmr2.ssp which framing bits are observed: f4: ft bits ? frs0.lfa f12, f72: ssp = 0: ft bits ? frs0.lfa: fs bits ? frs0.lfa and frs0.lmfa ssp = 1:ft ? frs0.lfa fs ? frs0.lmfa esf: esf framing bits ? frs0.lfa auto enable auto resynchronization 0 the receiver will not resynchronize automatically. starting a new synchronization procedure is possible via the bits: fmr0.exls or fmr0.frs. 1 auto-resynchronization is enabled. fm1fm0 select frame mode fm = 0: 12-frame multiframe format (f12, d3/4) fm = 1: 4-frame multiframe format (f4) fm = 2: 24-frame multiframe format (esf) fm = 3: 72-frame multiframe format (f72, remote switch mode) framer mode register 5 (read/write) value after reset: 00 h eibr enable internal bit robbing access 0 normal operation. 1 a one in this bit position will cause the transmitter to send the bit robbing signaling information stored in the xs1-12 (esf, f12, 72) registers in the corresponding time slots. xld transmit line loopback (llb) down code 0 normal operation. 1 a one in this bit position will cause the transmitter to replace normal transmit data with the llb down (deactuate) code 70 fmr5 eibr xld xlu xtm ssc2 (x21)
semiconductor group 303 09.98 peb 22554 operational description t1 / j1 continuously until this bit is reset. the llb down code will be optionally overwritten by the framing/dl/crc bits. xlu transmit llb up code 0 normal operation. 1 a one in this bit position will cause the transmitter to replace normal transmit data with the llb up (actuate) code continuously until this bit is reset. the llb up code will be optionally overwritten by the framing/dl/crc bits. for proper operation bit fmr5.xld must be cleared. xtm transmit transparent mode 0ports sypx / xmfs define the frame / multiframe begin on the transmit system highway. the transmitter is usually synchronized on this externally sourced frame boundary and generates the fs/dl bits according to this framing. any change of the transmit time-slot assignment will subsequently produce a change of the fs/dl bit positions. 1 disconnects the control of the transmit system interface from the transmitter. the transmitter is now in a free running mode without any possibility to actualize the multiframe position. the framing (fs/dl bits) generated by the transmitter will not be ?disturbed (in case of changing the transmit time-slot assignment) by the transmit system highway unless register xc1 is written. this bit should be set if loop-timed application is selected. for proper operation the transmit elastic buffer (2 frames, sic1.xbs1/0= 10) has to be enabled. ssc2 select sync conditions only valid in esf framing format. loss of frame alignment frs0.lfa is declared if more than 320 crc6 errors per second interval are detected.
semiconductor group 304 09.98 peb 22554 operational description t1 / j1 transmit control 0 (read/write) value after reset: 00 h brm enable bit robbing marker a one in this bit will mark the robbed bit positions on the system highway. rsigm marks the receive and xsigm marks the transmit robbed bits. mfbs enable pure multiframe begin signals only valid if esf or f72 format is selected. if set, signals rmfb and xmfb indicate only the multiframe begin. additional pulses (every 12 frames) are disabled. brfo bit robbing force one setting this bit forces the robbed bits high transmitted on port rdo. the received signaling data stream for the signaling controller is not influenced by this bit. xco10xco8 transmit offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse at port sypx or xmfs is active refer to register xc1. transmit control 1 (read/write) value after reset: 9c h a write access to this address resets the transmit elastic buffer to its basic starting position. therefore, updating the value should only be done when the quadfalc is initialized or when the buffer should be centered. as a consequence a transmit slip may occur. xto7xto0 transmit offset initial value loaded into the transmit bit counter at the trigger edge of sclkx when the synchronous pulse at port sypx / xmfs is active (see figure 55+56 ). 70 xc0 brm mfbs brfo xco10 xco8 (x22) 70 xc1 xto7 xto0 (x23)
semiconductor group 305 09.98 peb 22554 operational description t1 / j1 calculation of delay time t (sclkx cycles) depends on the value x of the ?transmit offset register xc1/0: system clocking rate: modulo 2.048 mhz (sic2.ssc2 = 0) 0 t 3 + (sc/sd) : x = 3 - t + (sc/sd) 4+ (sc/sd) t max. delay : x = 2051 - t + (sc/sd) with max. delay = (256 * sc/sd) -1 with sc = system clock defined by sic1.ssc1/0 + sic2.ssc2 with sd = system data rate or system clocking rate: modulo 1.544 mhz (sic2.ssc2 = 1) 0 t 3 + (7*sc/bf) + (sc/sd): --> x = 3 - t + (7*sc/bf) + ( sc/sd) 4 + (7*sc/bf) + (sc/sd) t max. delay : --> x = 3 - t + (200 * sc/bf) + (sc/sd) with max. delay = (200 * sc/sd) - (7*sc/sd) -1 with sc = system clock defined by sic1.ssc1/0 + sic2.ssc2 with sd = system data rate with bf = basic frequency = 1.544 mhz delay time t = time between beginning of time-slot 0 ( bit 0 , channel phase 0) at xdi / xsig and the initial edge of sclkx after sypx / xmfs goes active. receive control 0 (read/write) value after reset: 00 h sjr select japanese itu-t requirements 0 ? alarm handling is done according itu-t g. 704+706 1 ? alarm handling is done according itu-t jg. 704 + 706 rram receive remote alarm mode the conditions for remote (yellow) alarm (frs0.rra) detection can be selected via this bit to allow detection even in the presence of ber 10**-3: rram = 0 detection f4: bit2 = 0 in every speech channel per frame. f12: C fmr0.sraf = 0: bit2 = 0 in every speech channel per frame. 70 rco sjr rram crci xcrci rdis rco10 rco9 rco8 (x24)
semiconductor group 306 09.98 peb 22554 operational description t1 / j1 C fmr0.sraf = 1: s-bit of frame 12 is forced to 1 esf: C fmr0.sraf = 0: pattern 1111 1111 0000 0000 in data link channel C fmr0.sraf = 1: bit2 = 0 in every speech channel f72: bit2 = 0 in every speech channel per frame. release: the alarm will be reset when above conditions are no longer detected. rram = 1 (ber 10**-3 ) detection f4: bit2 = 0 in 255 consecutive speech channels. f12: C fmr0.sraf = 0: bit 2 = 0 in 255 consecutive speech channels. C fmr0.sraf = 1: s-bit of frame 12 is forced to 1 esf: C fmr0.sraf = 0: pattern 1111 1111 0000 0000 in data link channel C fmr0.sraf = 1: bit 2 = 0 in 255 consecutive speech channels f72: bit 2 = 0 in 255 consecutive speech channels. release depending on the selected multiframe format the alarm will be reset when quadfalc does not detect C the bit 2 = 0 condition for three consecutive pulseframes (all formats if selected), C the fs bit condition for three consecutive multiframes (f12), C the dl pattern for three times in a row (esf). crci automatic crc6 bit inversion if set, all crc bits of one outgoing extended multiframe are inverted in case a crc error is flagged for the previous received multiframe. this function is logically ored with rc0.xcrci. xcrci transmit crc6 bit inversion if set, the crc bits in the outgoing data stream are inverted before transmission. this function is logically ored with rc0.crci. rdis receive data input sense 0 ? inputs: rdip, rdin active low, input roid is active high 1 ? inputs: rdip, rdin active high, input roid is active low
semiconductor group 307 09.98 peb 22554 operational description t1 / j1 rco10rco8receive offset / receive frame marker offset depending on the rp(a-d) pin function different offsets could be programmed. the sypr and the rfm pin function could not be selected in parallel. receive offset (pc(1-4).rpc(2-0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 51 ). calculation of delay time t (sclkr cycles) depends on the value x of the ?receive offset register rc1/0. refer to register rc1. receive control 1 (read/write) value after reset: 9c h rto7rto0 receive offset / receive frame marker offset depending on the rp(a-d) pin function different offsets could be programmed. the sypr and the rfm pin function could not be selected in parallel. receive offset (pc(1-4).rpc(2-0) = 000) initial value loaded into the receive bit counter at the trigger edge of sclkr when the synchronous pulse at port sypr is active (see figure 51 ). calculation of delay time t (sclkr cycles) depends on the value x of the ?receive offset register rc1/0: system clocking rate: modulo 2.048 mhz (sic2.ssc2 = 0) 0 t 4 : x= 4- t 5 t max. delay : x= 2052 - t with max. delay = (256*sc/sd) -1 with sc = system clock defined by sic1.ssc1/0 + sic2.ssc2 with sd = 2.048 mhz or system clocking rate: modulo 1.544 mhz (sic2.ssc2 = 1) 0 t 4: x = 4- t + (7* sc/sd) 5 t max. delay : x = (200 * sc/sd) + 4 - t with max. delay = 193*sc/sd - 1 with sc = system clock defined by sic1.ssc1/0 + sic2.ssc2 with sd = 1.544 mhz 70 rc1 rto7 rto0 (x25)
semiconductor group 308 09.98 peb 22554 operational description t1 / j1 delay time t = time between beginning of time-slot 0 at rdo and the initial edge of sclkr after sypr goes active. receive frame marker offset (pc(1-4).rpc(2-0) = 001) offset programming of the receive frame marker which is output on multifunction port rfm. the receive frame marker could be activated during any bit position of the entire frame and depends on the selected system clock rate. calculation of the value x of the ?receive offset register rc1/0 depends on the bit position bp which should be marked : system clocking rate: modulo 2.048 mhz (sic2.ssc2 = 0) 0 bp 2045 : x= bp + 2 2046 bp 2047 : x= bp - 2046 ) e.g: 2.048 mbit/s: bp = 0-255; 4.096 mbit/s: bp = 0-511, 8.192 mbit/s: bp = 0-1023, 16.384 mbit/s: bp = 0-2047 system clocking rate: modulo 1.544 mhz (sic2.ssc2 = 1) 0 bp 193*(sc/sd) -3 : x = bp + 2 + 7*sc/sd 193*(sc/sd) -2 bp max. delay : x = bp + 2 - 186*sc/sd with max. delay = 193*sc/sd - 1 with sc = system clock defined by sic1.ssc1/0 + sic2.ssc2 with sd = 1.544 mhz transmit pulse-mask 20 (read/write) value after reset: 7b h , 03 h , 00 h the transmit pulse shape which is defined in ansi t1. 102 will be output on pins xl1 and xl2. the level of the pulse shape can be programmed via registers xpm2-0 to create a custom waveform. in order to get an optimized pulse shape for the external transformers each pulse shape will be internally devided into four sub pulse shapes. in each sub pulse shape a programmed 5 bit value will define the level of the analog voltage on pins xl1/2. together four 5 bit values have to be programmed to form one complete transmit pulse shape.the four 5 bit values will be sent in the following sequence: xp04-00: first pulse shape level xp14-10: second pulse shape level 70 x p m 0 x p 1 2 x p 1 1 x p 1 0 x p 0 4 x p 0 3 x p 0 2 x p 0 1 x p 0 0 ( x 2 6 ) xpm1 xp30 xp24 xp23 xp22 xp21 xp20 xp14 xp13 (x27) xpm2 xllp xlt daxlt xp34 xp33 xp32 xp31 (x28)
semiconductor group 309 09.98 peb 22554 operational description t1 / j1 xp24-20: third pulse shape level xp34-30: fourth pulse shape level changing the lsb of each subpulse in registers xpm2-0 will change the amplitude of the differential voltage on xl1/2 by approximately 80 mv. the xpm- values in the following table are based on simulations. they are valid for the following external circuitry: transformer ratio: 1:2.4; cable: pulb 22awg (100 w ); serial resistors: 2 w . adjustment of these coefficients may be necessary for other external conditions. ds1: the xpmxx register values shown in the table below are in decimal format. xlt transmit line tri-state 0 ? normal operation 1 ? transmit line xl1/xl2 or xdop/xdon are switched into high impedance state. if this bit is set the transmit line monitor status information will be frozen. daxlt... disable automatic tristating of xl1/2 0... normal operation. if a short is detected on pins xl1/2 the transmit line monitor will set the xl1/2 outputs into a high impedance state. 1... if a short is detected on pins xl1/2 an automatic setting these pins into a high impedance state (by the xl-monitor) will be disabled. xllp reserved 0 normal operation 1 reserved ( not to be used) range in m xp04-xp00 xp14-xp10 xp24-xp20 xp34-xp30 0 - 35 27 24 02 01 25 - 65 27 24 02 01 55 - 95 29 25 02 01 85 - 12529250301 115 - 155 29 25 04 01 145 - 185 29 26 04 02 175 - 210 29 27 05 02
semiconductor group 310 09.98 peb 22554 operational description t1 / j1 idle channel code register (read/write) value after reset: 00 h idl7idl0 idle channel code if channel loop back is enabled by programming the register loop.eclb = 1, the contents of the assigned outgoing channel at ports xl1/xl2 respective xdop/xdon is set equal to the idle channel code selected by this register. additionally, the specified pattern overwrites the contents of all channels of the outgoing pcm frame selected via the idle channel registers icb1icb3. idl7 will be transmitted first. transmit dl-bit register 1-3 (read/write) value after reset: 00 h , 00 h , 00 h xdl1xdl3 transmit fs/dl-bit data the dl-bit register access is enabled by setting bits fmr1.edl = 1. with the transmit multiframe begin an interrupt isr1.xmb is generated and the contents of these registers xdl1-3 will be copied into a shadow register. the contents will subsequently sent out in the data stream of the next outgoing multiframe if no transparent mode is enabled. xdl10 will be sent out first. in f4 frame format only xdl10+xdl11 will be transmitted. in f24 frame format xdl10-xdl23 will be shifted out. in f72 frame format xdl10-xdl37 will be transmitted. the transmit multiframe begin interrupt (xmb) requests that these registers should be serviced. if requests for new information will be ignored, current contents will be repeated. 70 idle idl7 idl0 (x2b) 70 xdl1 xdl17 xdl16 xdl15 xdl14 xdl13 xdl12 xdl11 xdl10 (x2c) xdl2 xdl27 xdl26 xdl25 xdl24 xdl23 xdl22 xdl21 xdl20 (x2d) xdl3 xdl37 xdl36 xdl35 xdl34 xdl33 xdl32 xdl31 xdl30 (x2e)
semiconductor group 311 09.98 peb 22554 operational description t1 / j1 clear channel register (read/write) value after reset: 00 h , 00 h , 00 h ch1ch24 channel selection bits 0 normal operation. bit robbing information and zero code suppression (zcs, b7 stuffing) may change contents of the selected speech/data channel if assigned modes are enabled via bits fmr5.eibr and fmr0.xc1/0. 1 clear channel mode. contents of selected speech/data channel will not be overwritten by internal or external bit robbing and zcs information. transmission of channel assigned signaling and control of pulse density is applied by the user. idle channel register (read/write) value after reset: 00 h , 00 h , 00 h , 00 h ic1ic24 idle channel selection bits these bits define the channels (time-slots) of the outgoing pcm frame to be altered. 0 normal operation. 1 idle channel mode. the contents of the selected channel is overwritten by the idle channel code defined via register idle. 70 ccb1 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 (x2f) ccb2 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 (x30) ccb3 ch17 ch18 ch19 ch20 ch21 ch22 ch23 ch24 (x31) 70 icb1 ic1 ic2 ic3 ic4 ic5 ic6 ic7 ic8 (x32) icb2 ic9 ic10ic11ic12ic13ic14ic15ic16(x33) icb3 ic17 ic18 ic19 ic20 ic21 ic22 ic23 ic24 (x34)
semiconductor group 312 09.98 peb 22554 operational description t1 / j1 line interface mode 0 (read/write) value after reset: 00 h xfb transmit full bauded mode only applicable for dual rail mode (bit lim1.drs = 1). 0output signals xdop/xdon are half bauded (normal operation). 1output signals xdop/xdon are full bauded. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. xdos transmit data out sense 0 output signals xdop/xdon are active low. output xoid is active high (normal operation). 1 output signals xdop/xdon are active high. output xoid is active low. note: if cmi coding is selected (fmr0.xc1/0=01) this bit has to be cleared. the transmit frame marker xfm is independent of this bit. eqon receive equalizer on 0 -10 db receiver: short haul mode 1 -36 db receiver: long haul mode ll local loop 0 ? normal operation 1 ? local loop active. the local loopback mode disconnects the receive lines rl1/rl2 respective rdip/rdin from the receiver. instead of the signals coming from the line the data provided by system interface are routed through the analog receiver back to the system interface. the unipolar bit stream will be undisturbed transmitted on the line. receiver and transmitter coding must be identical. operates in analog and digital line interface mode. in analog line interface mode data is transfered through the complete analog receiver. mas master mode 0 ? slave mode 70 lim0 xfb xdos eqon ll mas (x36)
semiconductor group 313 09.98 peb 22554 operational description t1 / j1 1 ? master mode on. setting this bit the dco-r circuitry is frequency synchronized to the clock (1.544 or 2.048 mhz) supplied by sync. if this pin is connected to vss or vdd the dco-r circuitry is centered and no receive jitter attenuation is performed. the generated clocks are stable. line interface mode 1 (read/write) value after reset: 00 h ril2ril0 receive input threshold only valid if analog line interface is selected (lim1.drs=0. no signal will be declared if the voltage between pins rl1 and rl2 drops below the limits programmed via bits ril2-0 and the received data stream has no transition for a period defined in the pcd register. the threshold where no signal will be declared is programmable via the ril2-0 bits depending of bit lim0.eqon. lim0.eqon = 0 (short haul mode): 000 = 0.9 v 001 = 0.7 v 010 = 0.6 v 011 = 0.4 v 100 = 0.3 v 101 = 0.2 v 110 = 0.07 v 111 = 0.05 v lim0.eqon = 1 (long haul mode): 000 = 1.7 v 001 = 0.8 v 010 = 0.8 v 011 = 0.5 v 100 = 0.5 v 101 = 0.2 v 110 = 0.1 v 111 = not assigned 70 lim1 ril2 ril1 ril0 dcoc jatt rl drs (x37)
semiconductor group 314 09.98 peb 22554 operational description t1 / j1 dcoc ? dco-r control 0 1.544 mhz reference clock for the dco-r circuitry provided on pin sync. 1 2.048 mhz reference clock for the dco-r circuitry provided on pin sync. jattrl... transmit jitter attenuator / remote loop 00 = normal operation. the transmit jitter attenuator is disabled. transmit data will bypass the buffer. 01 = remote loop active without transmit jitter attenuator enabled. transmit data will bypass the buffer. 10 = not assigned 11 = remote loop and jitter attenuator active. received data from pins rl1/2 or rdip/n or roid will be sent jitter free on ports xl1/2 or xdop/n or xoid. the dejittered clock is generated by the dco-x circuitry. drs dual rail select 0 = the ternary interface is selected. multifunction ports rl1/2 and xl1/2 become analog in/outputs. 1 = the digital dual rail interface is selected. received data is latched on multifunction ports rdip/rdin while transmit data is output on pins xdop/xdon. pulse count detection register (read/write) value after reset: 00 h pcd7pcd0 pulse count detection a los alarm (red alarm) will be detected if the incoming data stream has no transitions for a programmable number t consecutive pulse positions. the number t is programmable via the pcd register and can be calculated as follows: t= 16(n+1) ; with 0 =< n =< 255. the maximum time is: 256 16 648 ns = 2.65 ms. every detected pulse will reset the internal pulse counter. the counter will be clocked with the receive clock rclk. 70 pcd pcd7 pcd0 (x38)
semiconductor group 315 09.98 peb 22554 operational description t1 / j1 pulse count recovery (read/write) value after reset: 00 h pcr7pcr0 pulse count recovery a los alarm (red alarm) will be cleared if a pulse density is detected in the received bit stream.the number of pulses m which must occur in the predefined pcd time interval is programmable via the pcr register and can be calculated as follows: m = n+1 ; with 0 =< n =< 255. the time interval starts with the first detected pulse transition. with every received pulse a counter will be incremented and the actual counter is compared with the contents of pcr register. if the pulse number >= the pcr value the los alarm will be reset otherwise the alarm will still be active. in this case the next detected pulse transition will start a new time interval. an additional loss of signal recovery condition may be selected by register lim2.los1. line interface mode 2 (read/write) value after reset: 00 h lbo2...lbo1 line build-out in long haul applications lim0.eqon = 1 a transmit filter can be optionally placed on the transmit path to attenuate the data on pins xl1/2. selecting the transmitter attenuation is possible in steps of 7.5 db @772khz which is according to fcc 68 or ansi t1. 403. to meet the line build-out defined by ansi t1.403 registers xpm2-0 should be programmed as follows: 00 0 db 01 -7.5 db --> xpm2-0 = 20 h , 02 h , 51 h 10 -15 db --> xpm2-0 = 20 h , 01 h , 51 h 70 pcr pcr7 pcr0 (x39) 70 lim2 lbo2 lbo1 scf elt los1 (x3a)
semiconductor group 316 09.98 peb 22554 operational description t1 / j1 11 -22.5 db --> xpm2-0 = 20 h , 01 h , 50 h scf select corner frequency of dco-r setting this bit will reduce the corner frequency of the dco-r circuit by the factor of ten to 0.6 hz. note: reducing the corner frequency of the dco-r circuitry will increase the synchronization time before the frequencies are synchronized. elt enable loop-timed 0 normal operation 1 transmit clock is generated from the clock supplied by mclk which is synchronized to the extracted receive route clock. in this configuration the transmit elastic buffer has to be enabled. refer to register fmr5.xtm. for correct operation of loop timed the remote loop (bit lim1.rl = 0) must be inactive and bit cmr1.dxss must be cleared. los1 loss of signal recovery condition 0 the los alarm will be cleared if the predefined pulse density (register pcr) is detected during the time interval which is defined by register pcd. 1 additionally to the recovery condition described above a los alarm will only be cleared if the pulse density is fulfilled and no more than 15 contigious zeros are detected during the recovery interval. (according to tr-nwt 499). loop code register 1 (read/write) vaue after reset: 00 h eprm enable pseudo random bit sequence monitor 0 pseudo random bit sequence (prbs) monitor is disabled. 1 prbs is enabled. setting this bit enables incrementing the bit error counter bec with each detected prbs bit error. with any change of state of the prbs internal synchronization status an interrupt isr3.llbsc is generated. the current status of the prbs synchronizer is indicated by bit frs1.llbad. 70 lcr1 eprm xprbs ldc1 ldc0 lac1 lac0 fllb llbp (x3b)
semiconductor group 317 09.98 peb 22554 operational description t1 / j1 xprbs transmit pseudo random bit sequence a one in this bit position enables transmitting of a pseudo random bit sequence to the remote end. depending on pit llbp the prbs is generated according to 2 15 -1 or 2 20 -1 ( itu-t o. 151). ldc10... length deactuate (down) code these bits defines the length of the llb deactuate code which is programmable in register lcr2. 00 length: 5 bit 01 length: 6 bit, 2 bit, 3 bit 10 length : 7 bit 11 length : 8 bit, 2 bit, 4bit lac10... length actuate (up) code these bits defines the length of the llb actuate code which is programmable in register lcr3. 00 length: 5 bit 01 length: 6 bit, 2 bit, 3 bit 10 length : 7 bit 11 length : 8 bit, 2 bit, 4bit fllb framed line loopback / invert prbs depending on bit lcr1.xprbs this bit enables different functions: lcr1.xprbs=0: 0 the line loopback code is transmitted including framing bits. llb code overwrites the fs/dl bits. 1 the line loopback code is transmitted unframed. llb code will not overwrite the fs/dl bits. invert prbs lcr1.xprbs=1: 0 the generated prbs is transmitted not inverted. 1 the prbs is transmitted inverted. llbp line loopback pattern lcr1.xprbs=0 0 fixed line loopback code according to ansi t1. 403 . 1 enable user programmable line loopback code via register lcr2/3.
semiconductor group 318 09.98 peb 22554 operational description t1 / j1 lcr1.xprbs=1 or lcr1.eprm = 1 0 2 15 -1 1 2 20 -1 loop code register 2 (read/write) value after reset: 00 h ldc7ldc0 line loopback deactuate code if enabled by bit fmr5.xld the llb deactuate code will automatically repeat until the llb generator is stopped. transmit data is overwritten by the llb code. ldc0 is transmittted last. for correct operations bit lcr1.xprbs has to cleared. loop code register 3 (read/write) value after reset: 00 h lac7lac0 line loopback actuate code if enabled by bit fmr5.xlu the llb actuate code will automatically repeat until the llb generator is stopped. transmit data is overwritten by the llb code. lac0 is transmittted last. for correct operations bit lcr1.xprbs has to cleared. system interface control 1 (read/write) value after reset: 00 h ssc1...0 select system clock sic1.ssc1/0 and sic2.ssc2 define the clocking rate on the system highway. sic2.ssc2 = 0: 70 lcr2 ldc7 ldc0 (x3c) 70 lcr3 lac7 lac0 (x3d) 70 sic1 ssc1 ssd1 rbs1 rbs0 ssc0 bim xbs1 xbs0 (x3e)
semiconductor group 319 09.98 peb 22554 operational description t1 / j1 002.048 mhz 014.096 mhz 108.192 mhz 1116.384 mhz sic2.ssc2 = 1: 001.544 mhz 013.088 mhz 106.176 mhz 1112.352 mhz ssd1 select system data rate 1 sic1.ssd1, fmr1.ssd0 and sic2.ssc2 define the data rate on the system highway. programming ssd1/ssd0 and corresponding data rate is shown below. sic2.ssc2 = 0: 002.048 mbit/s 014.096 mbit/s 108.192 mbit/s 1116.384 mbit/s sic2.ssc2 = 1: 001.544 mbit/s 013.088 mbit/s 106.176 mbit/s 1112.352 mbit/s rbs1...0 receive buffer size 00 buffer size : 2 frames 01 buffer size : 1 frame 10 buffer size : 96 bits 11 by-pass of receive elastic store bim bit interleaved mode only applicable if bit sic2.ssc2 is cleared. if sic2.ssc2 is set high, the bit interleaved mode is automatically performed. 0byte interleaved mode 1bit interleaved mode
semiconductor group 320 09.98 peb 22554 operational description t1 / j1 xbs1...0 transmit buffer size 00 by-pass of transmit elastic store 01 buffer size : 1 frame 10 buffer size : 2 frames 11 buffer size : 96 bits system interface control 2 (read/write) value after reset: 00 h ffs force freeze signaling setting this bit disables updating of the receive signaling buffer and current signaling information is frozen. after resetting this bit and receiving a complete superframe updating of the signaling buffer is started again. the freeze signaling status could be also automatically generated by detecting the loss of signal alarm or a loss of frame alignment or a receive slip (only if external register access via rsig is enabled). this automatic freeze signaling function is logically ored with this bit. the current internal freeze signaling status is output on pin rp(a-d) / pin function freez which is selected by pc(1-4).rpc(2-0) = 110. additionally this status is also available in register sis.sfs. ssf serial signaling format only applicable if pin function r/xsig is selected. 0 bits 1-4 in all time-slots except time-slot 0 are cleared. 1 bits 1-4 in all time-slots except time-slot 0 are set high. crb center receive elastic buffer only applicable if the time-slot assigner is disabled ( pc1-4.rpc2-0 = 001 ) , no external or internal synchronous pulse receive is generated. a transition from low to high will force a receive slip and the read- pointer of the receive elastic buffer is centered. the delay through the buffer is set to one half of the current buffer size. it should be hold high for at least two 1.544 mhz periods before it is cleared. ssc2 select system clock 70 sic2 ffs ssf crb ssc2 sics2 sics1 sics0 (x3f)
semiconductor group 321 09.98 peb 22554 operational description t1 / j1 setting this bit together with sic1.ssc1/0 enables the system interface running with a clock of 1.544 , 3.088, 6.176 or 12.352 mhz. refer also to register sic1.ssc1/0. sics2 0 system interface channel select only applicable if the system clock rate is greater than 1.544 / 2.048mhz . received data is transmitted on pin rdo / rsig or received on xdi / xsig with the selected system data rate. if the data rate is greater than 1.544 / 2.048 mbit/s the data is output or sampled in half , a quarter or a 1/8 of the 125 sec. they will not be repeated. the time where the data is active during a 488 / 648 nsec time-slot is called in the following a channel phase. rdo / rsig are cleared while xdi / xsig are ignored for the remaining time of the 488 / 648 nsec or for the remaining channel phases. the channel phases are selectable with these bits. 000 data active in channel phase 1, valid if system data rate is 16 / 8 / 4 or 12 / 6 / 3 mbit/s 001 data active in channel phase 2, valid if data rate is 16 / 8 / 4 or 12 / 6 / 3 mbit/s 010 data active in channel phase 3, valid if data rate is 16 / 8 or 12 / 6 mbit/s 011 data active in channel phase 4, valid if data rate is 16 / 8 or 12 / 6 mbit/s 100 data active in channel phase 5 , valid if data rate is 16 or 12 mbit/s 101 data active in channel phase 6 , valid if data rate is 16 or 12 mbit/s 110 data active in channel phase 7, valid if data rate is 16 or 12 mbit/s 111 data active in channel phase 8 , valid if data rate is 16 or 12 mbit/s
semiconductor group 322 09.98 peb 22554 operational description t1 / j1 system interface control 3(read/write) value after reset: 00 h cmi select cmi precoding only valid if cmi code (fmr0.xc1/0=01) is selected. this bit defines the cmi precoding and influences only the transmit data and not the receive data. 0 cmi with b8zs precoding 1 cmi without b8zs precoding resx rising edge synchronous pulse transmit depending on this bit all transmit system interface data and marker are clocked off or sampled with the selected active edge. 0 sypx is latched with the first falling (active) edge of the sclkx clock. 1 sypx is latched with the first rising (active) edge of the sclkx clock. the sypx pin function is selected by pc(1-4).xc(2-0) = 0000. resr rising edge synchronous pulse receive depending on this bit all receive system interface data and marker are clocked off with the selected active edge. 0 sypr is latched with the first falling edge of the sclkr clock. 1 sypr is latched with the first rising edge of the sclkr clock. the sypr pin function is selected by pc(1-4).rpc(2-0) = 000. ttrf ttr register function setting this bit the function of the ttr1-4 registers are changed. a one in each ttr register will force the xsigm marker high for the respective time-slot and controls sampling of the time-slots provided by pin xsig. xsig is selected by pc(1-4).xpc(2-0). daf disable automatic freeze 0 signaling is automaticly frozen if one of the following alarms occured: loss of signal (frs0.los), loss of frame alignment (frs0.lfa) , or receive slips (isr3.rsp/n). 70 sic3 cmi resx resr ttrf daf (x40)
semiconductor group 323 09.98 peb 22554 operational description t1 / j1 1 automatic freezing of signaling data is disabled. updating of the signaling buffer is also done if one of the above described alarm conditions is active. however, updating of the signaling buffer is stopped if sic2.ffs is set. significant only if the serial signaling access is enabled. clock mode register 1 (read/write) value after reset: 00 h drss1 ... 0 dco-r synchronization clock source these bits select the reference clock source for the dco-r circuitry. 00 receive reference clock generated by the dpll of channel 1 01 receive reference clock generated by the dpll of channel 2 10 receive reference clock generated by the dpll of channel 3 11 receive reference clock generated by the dpll of channel 4 note: after reset all dco-r circuitries will synchronize on the clock sourced by the dpll of channel 1 . each channel have to be configured individually. if lim0.mas is set the dco-r circuitry will synchronize on the clock applied to port sync. rs1 ... 0 select rclk source these bits select the source of rclk. 00 extracted receive clock, generated by the dpll 01 extracted receive clock with the option in case of an active los alarm this pin is set high. 10 dejittered 1.544 or 2.048 mhz clock generated by the internal dco-r circuitry. the frequency depends on sic2.ssc2. 11 dejittered 6.176 or 8.192 mhz clock generated by the internal dco-r circuitry. the frequency depends on sic2.ssc2. dcs disable clock switching in slave mode (lim0.mas = 0) the dco-r is synchronized on the recovered route clock. in case of loss of signal los the dco-r 70 cmr1 drss1 drss0 rs1 rs0 dcs stf dxja dxss (x44)
semiconductor group 324 09.98 peb 22554 operational description t1 / j1 switches automatically to the clock sourced by port sync. setting this bit automatic switching from rclk to sync is disabled. stf select tclk frequency only applicable if the pin function tclk port xp(a-d) is selected by pc(1-4).xpc(2-0) = 011. data on xl1/2 , xdop/n, xoid are clocked off with tclk. 0 1.544 mhz 1 6.176 mhz dxja disable internal transmit jitter attenuation setting this bit disables the transmit jitter attenuation. reading the data out of the transmit elastic buffer and transmitting on xl1/2 (xdop/n / xoid) is done with the clock provided on pin tclk. in transmit elastic buffer bypass mode the transmit clock is taken from sclkx, independent of this bit. dxss dco-x synchronization clock source 0 the dco-x circuitry of each channel will synchronize to the internal reference clock which is sourced by sclkx/r or rclk. since there are many reference clock opportunities the following internal priorization in descenting order from left to right is realized: lim1.rl > cmr2.dxss > lim2.elt > current working clock of transmit system interface. if one of these bits is set the corresponding reference clock is taken. 1 dco-x synchronizes to an external reference clock provided by pin xp(a-d) pin function tclk, if no remote loop is active. tclk is selected by pc(1-4).xpc(2-0) = 011. clock mode register 2 (read/write) value after reset: 00 h dcf dco-r center- frequency disabled 0 the dco-r circuitry may be frequency centered - in master mode if no reference clock on pin sync is provided or - in slave mode if a loss of signal occurs in combination with no 70 cmr2 dcf irsp irsc ixsp ixsc (x45)
semiconductor group 325 09.98 peb 22554 operational description t1 / j1 clock on pin sync or - a gapped clock is provided at pin rclki and this clock is inactive or stopped. 1 the center function of the dco-r circuitry is disabled. the generated clock (dco-r) is frequency frozen in that moment when no clock is available at pin sync or pin rclki. the dco-r circuitry will starts synchronization as soon as a clock at pins sync or rclki appears. irsp internal receive system frame sync pulse 0 the frame sync pulse for the receive system interface is sourced by sypr . 1 the frame sync pulse for the receive system interface is internally sourced by the dco-r circuitry of each channel. this internally generated frame sync could be output active low on pin rp(a-d). rpc(2-0) = 001. programming the receive time-slot offset is also done in the same way as it is done for the external sypr . for correct operation bit irsc must be set. sypr is ignored. irsc internal receive system clock only applicable if bit gpc1.smm is cleared. if gpc1.smm is set sclkr1 of channel 1 provides the working clock for all four channels. 0 the working clock for the receive system interface is sourced by sclkr of each channel or in receive elastic buffer bypass mode from the corresponding extracted receive clock rclk. 1 the working clock for the receive system interface is sourced internally by dco-r or in bypass mode by the extracted receive clock of each channel. sclkr is ignored. ixsp internal transmit system frame sync pulse 0 the frame sync pulse for the transmit system interface is sourced by sypx . 1 the frame sync pulse for the transmit system interface is internally sourced by the dco-r circuitry of each channel. additionally, the external xmfs signal defines the transmit multiframe begin. xmfs is enabled or disabled via the multifunction ports. for correct operation bits cmr2.ixsc / irsc must be set. sypx is ignored. ixsc internal transmit system clock
semiconductor group 326 09.98 peb 22554 operational description t1 / j1 only applicable if bit gpc1.smm is cleared. if gpc1.smm is set sclkx1 of channel 1 provides the working clock for all four channels. 0 the working clock for the transmit system interface is sourced by sclkx of each channel. 1 the working clock for the transmit system interface is sourced internally by the working clock of the receive system interface. sclkx is ignored. global configuration register (read/write) value after reset: 00 h vis masked interrupts visible 0 masked interrupt status bits are not visible in registers isr0-4. 1 masked interrupt status bits are visible in isr0-4, but they are not visible in registers gis and cis. sci status change interrupt 0 interrupts will be generated either on coming or going of the internal interrupt source. 1 the following interrupts will be activated if enabled with detecting and recovering of the internal interrupt source: isr2.los , isr2.ais and isr0.pden ses select external second timer 0 internal second timer selected 1 external second timer selected ecmc error counter mode cofa 0 not defined; reserved for future applications. 1 a change of frame or multiframe alignment cofa is detected since the last re-synchronization. the events are accumulated in the cofa event counter coec.1-0. multiframe periods received in the asynchronous state are accumulated in the cofa event counter coec.7-2. an overflow of each counter is disabled. 70 gcr vis sci ses ecmc pd (x46)
semiconductor group 327 09.98 peb 22554 operational description t1 / j1 pd power down switches the appropriate single falc(1-4) between power up and power down mode. 0 power up 1 power down all outputs are driven inactive, except the multifunction ports, which are driven high. errored second mask (read/write) value after reset: ff h esm errored second mask this register functions as an additional mask register for the interrupt status bit errored second (isr3.es). a 1 in a bit position of esm sets the mask active for the interrupt status. disable error counter (write) value after reset: 00 h drbd disable receive buffer delay this bit has to be set before reading the register rbd. it will be automatically reset if rbd has been read. dcoec disable cofa event counter dbec disable prbs bit error counter only valid if lcr1.eprm=1 and fmr1.ecm are reset. 70 esm lfa fer cer ais los cve slip (x47) 70 dec drbd dcoec dbec dcec debc dcvc dfec (x60)
semiconductor group 328 09.98 peb 22554 operational description t1 / j1 dcec disable crc error counter debc disable errored block counter dcvc disable code violation counter dfec disable framing error counter these bits are only valid if fmr1.ecm is cleared. they have to be set before reading the error counters. they will be automatically reset if the corresponding error counter high byte has been read. with the rising edge of these bits the error counters are latched and then cleared.
semiconductor group 329 09.98 peb 22554 operational description t1 / j1 transmit signaling register (write) value after reset: not defined transmit signaling register 1-12 the transmit signaling register access is enabled by setting bit fmr5.eibr = 1. each register contains the bit robbing information for 8 ds0 channels. with the transmit cas empty interrupt isr1.case the contents of these registers will be copied into a shadow register. the contents will subsequently sent out in the corresponding bit positions of the next outgoing multiframe. xs1.7 will be sent out first in channel 1 frame 1 and xs12.0 will be sent out last. the transmit cas empty interrupt isr1.case requests that these registers should be serviced within the next 3 ms. if requests for new information are ignored, current contents will be repeated. if access to xs1-12 registers is done without control of the interrupt isr1.case and the write access to these registers is done exact in that moment when this interrupt is generated, data may be lost. note: a software reset (cmdr.xres) will reset these registers. 7 0 xs1 a1 b1 c1/a2 d1/b2 a2/a3 b2/b3 c2/a4 d2/b4 (x70) xs2 a3/a5 b3/b5 c3/a6 d3/b6 a4/a7 b4/b7 c4/a8 d4/b8 (x71) xs3 a5/a9 b5/b9 c5/a10 d5/b10 a6/a11 b6/b11 c6/a12 d6/b12 (x72) xs4 a7/a13 b7/b13 c7/a14 d7/b14 a8/a15 b8/b15 c8/a16 d8/b16 (x73) xs5 a9/a17 b9/b17 c9/a18 d9/b18 a10/a19 b10/b19 c10/a20 d10/b20 (x74) xs6 a11/a21 b11/b21 c11/a22 d11/b22 a12/a23 b12/b23 c12/a24 d12/b24 (x75) xs7 a13/a1 b13/b1 c13/a2 d13/b2 a14/a3 b14/b3 c14/a4 d14/b4 (x76) xs8 a15/a5 b15/b5 c15/a6 d15/b6 a16/a7 b16/b7 c16/a8 d16/b8 (x77) xs9 a17/a9 b17/b9 c17/a10 d17/b10 a18/a11 b18/b11 c18/a12 d18/b12 (x78) xs10 a19/a13 b19/b13 c19/a14 d19/b14 a20/a15 b20/b15 c20/a16 d20/b16 (x79) xs11 a21/a17 b21/b17 c21/a18 d21/b18 a22/a19 b22/b19 c22/a20 d22/b20 (x7a) xs12 a23/a21 b23/b21 c23/a22 d23/b22 a24/a23 b24/b23 c24/a24 d24/b24 (x7b)
semiconductor group 330 09.98 peb 22554 operational description t1 / j1 port configuration 1-4 (read/write) value after reset: 00 h rpc2 ...0 receive multifunction port configuration the multifunction ports rp(a-d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. the input function sypr may only be selected once, it should not be selected twice or more. register pc1 configures port rpa,while pc2 --> port rpb, pc3 --> port rpc and pc4 --> port rpd. 000sypr : synchronous pulse receive (input) together with register rc1/0 sypr defines the frame begin on the receive system interface. because of the offset programming the sypr and the rfm pin function could not be selected in parallel. 001rfm : receive frame sync (output) cmr2.irsp = 0: this receive frame marker could be active high for a 1.544 mhz or 2.048 mhz period during any bit position of the current frame. programming is done with registers rc1/0. the internal time-slot assigner is disabled. cmr2.irsp = 1: internal generated frame synchronization pulse generated by the dco-r circuitry. together with registers rc1/0 the frame begin on the receive system interface is defined. this frame synchronization pulse is active low 1.544 mhz or 2.048 mhz period. 010rmfb : receive multiframe begin (output) marks the beginning of every received multiframe or optionally every 12 frames (active high). 011rsigm : receive signaling marker (output) marks the time-slots which are defined by register rtr1-4 of every frame at port rdo. optionally in cas-br applications the robbed bits are marked every six frames. 70 pc1 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x80) pc2 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x81) pc3 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x82) pc4 rpc2 rpc1 rpc0 xpc2 xpc1 xpc0 (x83)
semiconductor group 331 09.98 peb 22554 operational description t1 / j1 100rsig : receive signaling data (output) the received cas multiframe is transmitted on this pin. time-slots on rsig correlates directly to the time-slot assignment on rdo. in system interface multiplex mode all four received signaling data streams are merged into a single rail data stream byte or bit interleaved on rsig1. 101dlr : data link bit receive (output) marks the dl-bit position within the data stream on rdo. 110freez : freeze signaling (output) the freeze signaling status is active high by detecting a loss of signal alarm, or a loss of frame alignment or a receive slip (pos. or neg.). it will hold high for at least one complete multiframe after the alarm disappears. setting sic2.ffs enforces a high on pin freez. 111rfsp : receive frame synchronous pulse (output) marks the frame begin in the receivers synchrounous state. this marker is active low for 648 ns with a frequency of 8 khz. xpc2 ...0 transmit multifunction port configuration the multifunction ports xp(a-d) are bidirectional. after reset these ports are configured as inputs. with the selection of the pin function the in/output configuration is also achieved. each of the four different input functions ( sypx , xmfs, xsig, tclk ) may only be selected once. no input function should be selected twice or more. sypx and xmfs should not be selected in parallel. register pc1 configures port xpa,while pc2 --> port xpb, pc3 --> port xpc and pc4 --> port xpd. 000sypx : synchronous pulse transmit (input) together with register xc1/0 sypx defines the frame begin on the transmit system interface ports xdi and xsig. 001xmfs : transmit multiframe synchronization (input) together with register xc1/0 xmfs defines the frame and multiframe begin on the transmit system interface ports xdi and xsig. depending on pc5.cxmfs the signal on xmfs is active high or low. 010xsig : transmit signaling data (input) input for transmit signaling data received from the signaling highway. in system interface multiplex mode latching of the data stream containing the 4 signaling multiframes is done byte or bit interleaved on port xdi1. optionally sampling of xsig data is controlled by the active high xsigm marker.
semiconductor group 332 09.98 peb 22554 operational description t1 / j1 011tclk : transmit clock (input) a 1.544 / 6.176 mhz clock has to be sourced by the system if the internal generated transmit clock (dco-x) should not be used. optionally this input functions as a synchronization clock for the dco-x circuitry with a frequencyof 1.544 mhz. 100xmfb : transmit multiframe begin (output) marks the beginning of every transmit multiframe or optionally every 12 frames. 101xsigm : transmit signaling marker (output) marks the time-slots which are defined by register ttr1-4 of every frame at port xdi. optionally in cas-br applications the robbed bits are marked every six frames. 110dlx : data link bit transmit (output) marks the dl-bit position within the data stream on xdi. 111xclk : transmit line clock (output) frequency: 1.544 mhz port configuration 5 (read/write) value after reset: 00 h cxmfs configure xmfs port 0 port xmfs is active low. 1 port xmfs is active high. csxp configure sclkx port 0 sclkx : input 1 sclkx : output csrp configure sclkr port 0 sclkr : input 1 sclkr : output crp configure rclk port 0 rclk : input 1 rclk : output 70 pc5 cxmfs csxp csrp crp (x84)
semiconductor group 333 09.98 peb 22554 operational description t1 / j1 global port configuration 1 (read/write) value after reset: 00 h smm system interface multiplex mode setting this bit enables a single rail data stream of 16.384 / 8.192 / 12.352 or 6.176 mbit/s containg all four t1 frames. the receive system interface for all four channels is running with the clock provided on sclkr1 and the frame sync pulse provided on sypr1 . the transmit system interface is running with sclkx1 and sypx1 . data will be transmitted / accepted in a byte or bit interleaved format. bit interleaving is valid with the 16.384 / 8.192 / 12.352 or 6.176 mhz clocking rates. however byte interleaving is only applicable with the 16.384 or 8.192 mhz clock. in the system interface multiplex mode the following pin configuration has to be fulfilled and must be identically for all for 4 channels: - sypr1 has to be provided on pin rpa1 - sypx1 has to be provided on pin xpa1 or - xmfs has to be provided on pin xpb1 - xsig has to be provided on pin xpc1 - rsig will be output on pin rpb1 each of the four channels have to be configured equally: - clocking rate : 16.384 / 8.192 / 12.352 mhz or 6.176 mhz sic1.ssc1/0 and sic2.ssc2 - data rate : 16.384 / 8.192 / 12.352mbit/s or 6.176 mbit/s, sic1.ssd1, fmr1.ssd0 - time-slot offset programming : rc1/0 , xc1/0 - receive buffer size : sic1.rbs1/0 = 00 (2 frames) e.g. : system clock rate = 8.192 mhz : sic1.ssc1/0 = 10 and system data rate = 8.192 mbit/s : sic1.ssd1 = 1 , fmr1.ssd0 = 0 the multiplexed data stream is internal logically ored. therefore the selection of the active channel phase have to be configured different for each single channel falc(1-4). programming is done with sic2.sics2-0. for falc1: sic2.sics2-0 = 000, selects the first channel phase for falc2: sic2.sics2-0 = 001, selects the second channel phase 70 gpc1 smm csfp1 csfp0 fss1 fss0 r1s1 r1s0 (85)
semiconductor group 334 09.98 peb 22554 operational description t1 / j1 for falc3: sic2.sics2-0 = 010, selects the third channel phase for falc4: sic2.sics2-0 = 011, selects the fourth channel phase byte interleaved data format: sic1.bim = 0 xdi/rdo: f1-ts0, f2-ts0, f3-ts0, f4-ts0, f1-ts1, ... f4-ts31 x/rsig: f1-sts0, f2-sts0, f3-sts0, f4-sts0, f1-... f4-sts31 or : bit interleaved data format: sic1.bim = 1 xdi/rdo: f1-ts0-b1, f2-ts0-b1, f3-ts0-b1, f4-ts0-b1, f1-ts0-b2, ... f4-ts31-b8 x/rsig: f1-sts0-b1, f2-sts0-b1, f3-sts0-b1, f4-sts0-b1, f1- sts0-b2, ... f4-sts31-b8 with : f = framer, ts = time-slot, sts = signaling time-slot, b = bit in system interface multiplex mode signals on rdo2-4 and rsig2-4 are undefined, while signals on sclkr2-4, sypr 2-4, sclkx2-4, sypx 2-4, xdi2-4 and xsig2-4 are ignored. csfp1 ... 0 configure sec / fsc port the fsc pulse is generated if the dco-r circuitry of the selected channel is active (cmr2.irsc = 1 or cmr1.rs1/0 = 10 or 11). 00 sec : input , active high 01 sec : output, active high 10 fsc: output , active high 11 fsc: output, active low fss1 ... 0 sec / fsc source one of the four internal generated dejittered 8 khz clocks or second timers (sec) are output on port sec / fsc. gpc1.csfp1 = 1: 00 fsc : 8 khz sourced by channel 1 01 fsc : 8 khz sourced by channel 2 10 fsc : 8 khz sourced by channel 3 11 fsc : 8 khz sourced by channel 4 gpc1.csfp1 = 0: 00 sec : second timer sourced by channel 1 01 sec: second timer sourced by channel 2 10 sec: second timer sourced by channel 3
semiconductor group 335 09.98 peb 22554 operational description t1 / j1 11 sec: second timer sourced by channel 4 r1s1 ... 0 rclk1 source one of the four internal generated receive route clocks are output on port rclk1. outputs rclk2-4 are valid independent of these bits. refer to bit cmr1.rs1/0. 00 extracted receive clock of channel 1 01 extracted receive clock of channel 2 10 extracted receive clock of channel 3 11 extracted receive clock of channel
semiconductor group 336 09.98 peb 22554 operational description t1 / j1 8.5 status register description table 31 status register address arrangement address register type comment 00 100 200 300 rfifo r receive fifo 49 149 249 349 rbd r receive buffer delay 4a vstr r version status 4b 14b 24b 34b res r receive equalizer status 4c 14c 24c 34c frs0 r framer receive status 0 4d 14d 24d 34d frs1 r framer receive status 1 4e 14e 24e 34e frs2 r framer receive status 2 4f 14f 24f 34f 50 150 250 350 fecl r framing error counter low 51 151 251 351 fech r framing error counter high 52 152 252 352 cvcl r code violation counter low 53 153 253 353 cvch r code violation counter high 54 154 254 354 cecl r crc error counter low 55 155 255 355 cech r crc error counter high 56 156 256 356 ebcl r errored block counter low 57 157 257 357 ebch r errored block counter high 58 158 258 358 becl r bit error counter low 59 159 259 359 bech r bit error counter high 5a 15a 25a 35a coec r cofa event counter 5b 15b 25b 35b 5c 15c 25c 35c rdl1 r receive dl-bit register 1 5d 15d 25d 35d rdl2 r receive dl-bit register 2 5e 15e 25e 35e rdl3 r receive dl-bit register 3 5f 15f 25f 35f 60 160 260 360 61 161 261 361 62 162 262 362 rsp1 r receive signaling pointer 1 63 163 263 363 rsp2 r receive signaling pointer 2
semiconductor group 337 09.98 peb 22554 operational description t1 / j1 64 164 264 364 sis r signaling status register 65 165 265 365 rsis r receive signaling status register 66 166 266 366 rbcl r receive byte control low 67 167 267 367 rbch r receive byte control high 68 168 268 368 isr0 r interrupt status register 0 69 169 269 369 isr1 r interrupt status register 1 6a 16a 26a 36a isr2 r interrupt status register 2 6b 16b 26b 36b isr3 r interrupt status register 3 6c 16c 26c 36c isr4 r interrupt status register 4 6d 16d 26d 36d 6e 16e 26e 36e gis r global interrupt status 6f cis r channel interrupt status 70 170 270 370 rs1 r receive signaling register 1 71 171 271 371 rs2 r receive signaling register 2 72 172 272 372 rs3 r receive signaling register 3 73 173 273 373 rs4 r receive signaling register 4 74 174 274 374 rs5 r receive signaling register 5 75 175 275 375 rs6 r receive signaling register 6 76 176 276 376 rs7 r receive signaling register 7 77 177 277 377 rs8 r receive signaling register 8 78 178 278 378 rs9 r receive signaling register 9 79 179 279 379 rs10 r receive signaling register 10 7a 17a 27a 37a rs11 r receive signaling register 11 7b 17b 27b 37b rs12 r receive signaling register 12 8.5 status register description table 31 status register address arrangement address register type comment
semiconductor group 338 09.98 peb 22554 operational description t1 / j1 receive fifo (read) rfifo reading data from rfifo can be done in an 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. the size of the accessible part of rfifo is determined by programming the bits ccr1.rft1 ? 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). data transfer up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (32, 16, 4, 2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the receive message complete command (rmc). receive buffer delay (read) rbd5rbd0... receive elastic buffer delay these bits informs the user about the current delay (in time-slots) through the receive elastic buffer. the delay is updated every 386 or 193 bits (sic1.rbs1/0). before reding this register the user has to set bit dec.drbd in order to halt the current value of this register. after reading rbd updating of this register is enabled. not valid if the receive buffer is bypassed. 000000 = delay < 1 time-slot : : 111111 = delay >63 time-slots 70 rfifo rf7 rf0 (x00/x01) 70 rbd rbd5 rbd4 rbd3 rbd2 rbd1 rbd0 (x49)
semiconductor group 339 09.98 peb 22554 operational description t1 / j1 version status register (read) vn7 C vn0 version number of chip 00 h version 1.1 receive equalizer status (read) ev1ev0... equalizer status valid these bits informs the user about the current state of the receive equalization network . only vaild if lim1.eqon is set. 00 equalizer status not vaild, still adapting 01 equalizer status vaild 10 equalizer status not vaild 11 equalizer status valid but high noise floor res4res0... receive equalizer status the current line attenuation status in steps of nearly 1.4 db are displayed in these bits. only valid if bits ev1/0 = 01. accuracy: +/- 2 digit, based on temperature influence and noise amplitude variations. 00000 attenuation: 0 db ... 11001 max. attenuation: -36 db 70 vstr vn7 vn0 (4a) 70 res ev1 ev0 res4 res3 res2 res1 res0 (x4b)
semiconductor group 340 09.98 peb 22554 operational description t1 / j1 framer receive status register 0 (read) los loss of signal (red alarm) detection: this bit is set when the incoming signal has ?no transitions (analog interface) or logical zeros (dig. interface) in a time interval of t consecutive pulses, where t is programmable via pcd register: total account of consecutive pulses: 16 < t < 4096. analog interface: the receive signal level where no transition will be declared is defined by the programmed value of lim1.ril2-0. recovery: analog interface: the bit will be reset in short haul mode when the incoming signal has transitions with signal levels greater than the programmed receive input level (lim1.ril2-0) for at least m pulse periods defined by register pcr in the pcd time interval. in long haul mode addtionally bit res.6 must be set for at least 250sec. digital interface: the bit will be reset when the incoming data stream contains at least m ones defined by register pcr in the pcd time interval. with the rising edge of this bit an interrupt status bit (isr2.los) will be set. for additionally recovery conditions refer also to register lim2.los1. the bit will be set during alarm simulation and reset if frs2.esc = 0, 3, 4, 6,7 and no alarm condition exists. ais alarm indication signal (blue alarm) this bit is set when the conditions defined by bit fmr4.ais3 are detected. the flag stays active for at least one multiframe. with the rising edge of this bit an interrupt status bit (isr2.ais) will be set. it will be reset with the beginning of the next following multiframe if no alarm condition is detected. the bit will be set during alarm simulation and reset if frs2.esc = 0, 3, 4, 7 and no alarm condition exists. lfa loss of frame alignment the flag is set if pulseframe synchronization has been lost. the conditions are specified via bit fmr4.ssc1/0. setting this bit will cause an interrupt status (isr2.lfa). 70 frs0 los ais lfa rra lmfa fsrf (x4c)
semiconductor group 341 09.98 peb 22554 operational description t1 / j1 the flag is cleared when synchronization has been regained. additionally interrupt status isr2.far is set with clearing this bit. rra receive remote alarm (yellow alarm) the flag is set after detecting remote alarm (yellow alarm). conditions for setting/resetting are defined by bit rc0.rram. with the rising edge of this bit an interrupt status bit isr2.ra will be set. with the falling edge of this bit an interrupt status bit isr2.rar will be set. the bit will be set during alarm simulation and reset if frs2.esc = 0, 3, 4,5,7 and no alarm condition exists. lmfa loss of multiframe alignment set in f12 or f72 format when 2 out of 4- (or 5 or 6) multiframe alignment patterns are incorrect. additionally the interrupt status bit isr2.lmfa is set. cleared after multiframe synchronization has been regained. with the falling edge of this bit an interrupt status bit isr2.mfar is generated. fsrf frame search restart flag toggles when no framing candidate (pulseframing or multiframing) is found and a new frame search is started.
semiconductor group 342 09.98 peb 22554 operational description t1 / j1 framer receive status register 1 (read) exzd excessive zeros detected significant only if excessive zeros detection is enabled (fmr2.exze=1). set after detecting of more than 7 (b8zs code) or more than 15 (ami code) contiguous zeros in the received bit stream. this bit is cleared when read. pden pulse density violation detected the pulse density of the received data stream is below the requirement defined by ansi t1. 403 or more than 14 consecutive zeros are detected. with the violation of the pulse density this bit will be set and will remain active until it is read. reading the register will clear this bit. (clear on read). additionally an interrupt status isr0.pden is generated with the rising edge of pden. llbdd line loop back deactuation signal detected this bit is set to one in case the llb deactuate signal is detected and then received over a period of more than 33,16 msec with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit will cause a llbsc interrupt. llbad line loopback actuation signal detected / prbs status depending on bit lcr1.eprm the source of this status bit changed. lcr1.eprm=0: this bit is set to one in case the llb actuate signal is detected and then received over a period of more than 33,16 msec with a bit error rate less than 1/100. the bit remains set as long as the bit error rate does not exceed 1/100. if framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. any change of this bit will cause a llbsc interrupt. 70 frs1 exzd pden llbdd llbad xls xlo (x4d)
semiconductor group 343 09.98 peb 22554 operational description t1 / j1 prbs status lcr1.eprm=1: the current status of the prbs synchronizer is indicated in this bit. it is set high if the synchronous state is reached even in the presence of a ber 1/10. a data stream containing all zeros with / without framing bits is also a valid pseudo random bit sequence. xls transmit line short significant only if the ternary line interface is selected by lim1.drs=0. 0 normal operation. no short is detected. 1 the xl1 and xl2 are shortend for at least 3 pulses. as a reaction of the short the pins xl1 and xl2 are automatically forced into a high impedance state if bit xpm2.daxlt is reset. after 128 consecutive pulse periods the outputs xl1/2 are activated again and the internal transmit current limiter is checked. if a short between xl1/2 is still further active the outputs xl1/2 are in high impedance state again. when the short disappears pins xl1/2 are activated automatically and this bit will be reset. with any change of this bit an interrupt isr1.xlsc will be generated. in case of xpm2.xlt is set this bit will be frozen. xlo transmit line open 0 normal operation 1 this bit will be set if at least 32 consecutive zeros were sent via pins xl1/xl2 respective xdop/xdon. this bit is reset with the first transmitted pulse. with the rising edge of this bit an interrupt isr1.xlsc will be set. in case of xpm2.xlt is set this bit will be frozen.
semiconductor group 344 09.98 peb 22554 operational description t1 / j1 framer receive status register 2 (read) esc2esc0 error simulation counter this three-bit counter is incremented by setting bit fmr0.sim. the state of the counter determines the function to be tested: for complete checking of the alarm indications, eight simulation steps are necessary (frs2.esc = 0 after a complete simulation). some of these alarm indications are simulated only if the quadfalc is configured in the appropriate mode. at simulation steps 0, 3, 4, and 7 pending status flags are reset automatically and clearing of the error counters and interrupt status registers isr0-3 should be done. incrementing the simulation counter should not be done at time intervals 70 frs2 esc2 esc0 (x4e) tested alarms esc2esc0 = 0 1234567 lfa x x lmfa x x rra (bit2 =0) x rra (s-bit fr. 12) x rra (dl-pattern) x los x x x ebc (f12,f72) x x ebc (only esf) x x x x ais x x x x fec x x cvc x x x cec (only esf) xx xx rsp x rsn x xsp x xsn x bec xx x coec xx
semiconductor group 345 09.98 peb 22554 operational description t1 / j1 shorter than 1.5 ms (f4, f12, f72) or 3 ms (esf). otherwise, reactions of initiated simulations may occur at later steps. framing error counter (read) fe15fe0 framing errors this 16-bit counter will be incremented when incorrect ft and fs bits in f4, f12 and f72 format or incorrect fas bits in esf format are received. framing errors will not be counted during asynchronous state. the error counter will not roll over. during alarm simulation, the counter will be incremented twice. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dfec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dfec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 fecl fe7 fe0 (x50) 70 fech fe15 fe8 (x51)
semiconductor group 346 09.98 peb 22554 operational description t1 / j1 code violation counter (read) cv15cv0 code violations no function if nrz code has been enabled. if the b8zs code (bit fmr0.rc1/0 = 11) is selected, the 16-bit counter will be incremented by detecting violations which are not due to zero substitution. if fmr2.exze is set, additionally excessive zero strings (more than 7 contiguous zeros) are detected and counted. if simple ami coding is enabled (fmr0.rc0/1 = 10) all bipolar violations are counted. if fmr2.exze is set, additionally excessive zero strings (more than 15 contiguous zeros) are detected and counted. the error counter will not roll over. during alarm simulation, the counter is incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcvc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcvc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cvcl cv7 cv0 (x52) 70 cvch cv15 cv8 (x53)
semiconductor group 347 09.98 peb 22554 operational description t1 / j1 crc error counter (read) cr15cr0 crc errors no function if crc6 procedure or esf format are disabled. in esf mode, the 16-bit counter will be incremented when a multiframe has been received with a crc error. crc errors will not be counted during asynchronous state. the error counter will not roll over. during alarm simulation, the counter is incremented once per multiframe. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.dcec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 cecl cr7 cr0 (x54) 70 cech cr15 cr8 (x55)
semiconductor group 348 09.98 peb 22554 operational description t1 / j1 errored block counter (read) ebc15ebc0 errored block counter in esf format this 16-bit counter will be incremented once per multiframe if a multiframe has been received with a crc error or an errored frame alignment has been detected. crc and framing errors will not be counted during asynchronous state. the error counter will not roll over. in f4/12/72 format an errored block contain 4/12 or 72 frames. incrementing is done once per multiframe if framing errors has been detected. during alarm simulation, the counter is incremented in esf format once per multiframe and in f4/12/72 format only one time. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the error counter bit dec.debc has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.debc will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 ebcl ebc7 ebc0 (x56) 70 ebch ebc15 ebc8 (x57)
semiconductor group 349 09.98 peb 22554 operational description t1 / j1 bit error counter (read) bec15bec0 bit error counter if the prbs monitor is enabled by lcr1.eprm= 1 this 16-bit counter will be incremented with every received prbs bit error in the prbs synchronous state frs1.llbad=1. the error counter will not roll over. during alarm simulation, the counter will be incremented continuously with every second received bit. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the prbs bit error counter bit dec.dbec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dbec will automatically be reset with reading the error counter high byte. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 becl bec7 bec0 (x58) 70 bech bec15 bec8 (x59)
semiconductor group 350 09.98 peb 22554 operational description t1 / j1 cofa event counter (read) coe7coe2 multiframe counter if gcr.ecmc = 1 this 6 bit counter increments with each multiframe period in the asynchronous state frs0.lfa/lmfa =1. the error counter will not roll over. coe1coe0 change of frame alignment counter if gcr.ecmc = 1 this 2 bit counter increments with each detected change of frame / multiframe alignment. the error counter will not roll over. during alarm simulation, the counter is incremented once per multiframe. clearing and updating the counter is done according to bit fmr1.ecm. if this bit is reset the error counter is permanently updated in the buffer. for correct read access of the event counter bit dec.dcoec has to be set. with the rising edge of this bit updating the buffer will be stopped and the error counter will be reset. bit dec.dcoec will automatically be reset with reading the error counter high byte on address 5b h . data read on 5b h is not defined. if fmr1.ecm is set every second (interrupt isr3.sec) the error counter will be latched and then automatically reset. the latched error counter state should be read within the next second. 70 coec coe7 coe2 coe1 coe0 (x5a)
semiconductor group 351 09.98 peb 22554 operational description t1 / j1 receive dl-bit register 1 (read) rdl17rdl10receive dl-bit only valid if f12, f24 or f72 format is enabled. the received fs/dl-bits are shifted into this register. rdl10 is received in frame 1 and rdl17 in frame 15, if f24 format is enabled. rdl10 is received in frame 26 and rdl17 in frame 40, if f72 format is enabled. in f12 format the fs-bits of a complete multiframe is stored in this register. rdl10 is received in frame 2 and rdl15 in frame 12. this register will be updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 2 (read) rdl27rdl20receive dl-bit only valid if f24 or f72 format is enabled. the received dl-bits are shifted into this register. rdl20 is received in frame 17 and rdl23 in frame 23, if f24 format is enabled. rdl20 is received in frame 42 and rdl27 in frame 56, if f72 format is enabled. this register will be updated with every receive multiframe begin interrupt isr0.rmb. receive dl-bit register 3 (read) rdl37rdl30receive dl-bit only valid if f72 format is enabled. the received dl-bits are shifted into this register. rdl30 is received in frame 58 and rdl37 in frame 72, if f72 format is enabled. this register will be updated with every receive multiframe begin interrupt isr0.rmb. 70 rdl1 rdl17 rdl16 rdl15 rdl14 rdl13 rdl12 rdl11 rdl10 (x5c) 70 rdl2 rdl27 rdl26 rdl25 rdl24 rdl23 rdl22 rdl21 rdl20 (x5d) 70 rdl3 rdl37 rdl30 (x5e)
semiconductor group 352 09.98 peb 22554 operational description t1 / j1 receive signaling pointer 1 (read) value after reset: 00 h rs8crs1c receive signaling register rs1-8 changed a one in each bit position indicates that the received signaling data in the corresponding rs1-8 registers are updated. bit rs1c is the pointer for register rs1,... while rs8c points to rs8. receive signaling pointer 2 (read) value after reset: 00 h rs12crs9c receive signaling register rs9-12 changed a one in each bit position indicates that the received signaling data in the corresponding rs9-12 registers are updated. bit rs9c is the pointer for register rs9,... while rs12c points to rs12 70 rsp1 rs8c rs7c rs6c rs5c rs4c rs3c rs2c rs1c (x62) 70 rsp2 rs12c rs11c rs10c rs9c (x63)
semiconductor group 353 09.98 peb 22554 operational description t1 / j1 signaling status register (read) xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres or C when all bytes in the accessible half of the xfifo have been moved in the inaccessible half. xfw transmit fifo write enable data can be written to the xfifo. xrep transmission repeat status indication of cmdr.xrep. ivb invalid bom frame received 0 ? valid bom frame (11111111, 0xxxxxx0) received. 1 ? invalid bom frame received. rli receive line inactive neither flags as interframe time fill nor frames are received via the signaling timeslot. cec command executing 0 ? no command is currently executed, the cmdr register can be written to. 1 ? a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 2.5 periods of the current system data rate. sfs status freeze signaling 0 freeze signaling status inactive. 1 freeze signaling status active. 70 sis xdov xfw xrep ivb rli cec sfs bom (x64)
semiconductor group 354 09.98 peb 22554 operational description t1 / j1 bom bit oriented message significant only in esf frame format and auto switching mode is enabled. 0 hdlc mode 1 bom mode receive signaling status register (read) rsis relates to the last received hdlc or bom frame; it is copied into rfifo when end-of-frame is recognized (last byte of each stored frame). vfr valid frame determines whether a valid frame has been received. 1 ? valid 0 ? invalid an invalid frame is either C a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or C a frame which is too short taking into account the operation mode selected via mode (mds2-0) and the selection of receive crc on/off (ccr2.rcrc) as follows: ? mds2-0 = 011 (16 bit address), rcrc = 0 : 4 bytes; rcrc = 1 : 3-4 bytes ? mds2-0 = 010 (8 bit address), rcrc = 0 : 3 bytes; rcrc = 1 : 2-3 bytes note: shorter frames are not reported. rdo receive data overflow a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/imr1.rdo). crc16 crc16 compare/check 0 ? crc check failed; received frame contains errors. 1 ? crc check o.k.; received frame is error-free. 70 rsis vfr rdo crc16 rab ha1 ha0 hfr la (x65)
semiconductor group 355 09.98 peb 22554 operational description t1 / j1 rab receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. ha1, ha0 high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the quadfalc compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: 00 rah2 has been recognized 01 broadcast address has been recognized 10 rah1 has been recognized c/r = 0(bit 1) 11 rah1 has been recognized c/r = 1 (bit 1) note: if rah1, rah2 contain identical values, a match is indicated by 10or 11. hfr hdlc frame format 0 ? a bom frame was received. 1 ? a hdlc frame was received. note: rsis 7-2, 0 is not valid with a bom frame. la low byte address compare significant in hdlc modes only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 ? ral2 has been recognized 1 ? ral1 has been recognized
semiconductor group 356 09.98 peb 22554 operational description t1 / j1 receive byte count low (read) together with rbch (bits rbc11 - rbc8), indicates the length of a received frame (1 ? 4095 bytes). bits rbc4-0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. received byte count high (read) value after reset: 000 xxxxx ov counter overflow more than 4095 bytes received. rbc11 C rbc8 ? receive byte count (most significant bits) together with rbcl (bits rbc7 ? rbc0) indicate the length of the received frame. interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. if bit gcr.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. rme receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. 70 rbcl rbc7 rbc0 (x66) 70 rbch ov rbc11 rbc8 (x67) 70 isr0 rme rfs/biv isf rmb rsc crc6 pden rpf (x68)
semiconductor group 357 09.98 peb 22554 operational description t1 / j1 the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc4-0. additional information is available in the rsis register. rfs / biv receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after a rfs interrupt, the contents of ral1and rsis.3-1 are valid and can be read by the cpu. bom frame invalid only valid if ccr2.rbfe is set. when the bom receiver left the valid bom status (detecting 7 out of 10 equal bom frames) this interrupt is generated. isf incorrect sync format the quadfalc could not detect eight consecutive ones within 32 bits in bom mode. only valid if bom receiver has been activated. rmb receive multiframe begin this bit is set with the beginning of a received multiframe of the receive line timing. rsc received signaling information changed this interrupt bit is set during each multiframe in which signaling information on at least one channel changes its value from the previous multiframe. this interrupt will only occur in the synchronous state. the registers rs1-12 should be read within the next 3 ms otherwise the contents may be lost. crc6 receive crc6 error 0 no crc6 error occurs. 1 the crc6 check of the last received multiframe failed. pden pulse density violation the pulse density violation of the received data stream defined by ansi t1. 403 is violated. more than 14 consectuive zeros or less than n ones in each and every time window of 8(n+1) data bits (n=23) are detected. if gcr.sci is set high this interrupt status bit will be activated with every change of state of frs1.pden.
semiconductor group 358 09.98 peb 22554 operational description t1 / j1 rpf receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. interrupt status register 1 (read) all bits are reset when isr1 is read. if bit gcr.vis is set to 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. case transmit cas register empty in esf format this bit is set with the beginning of a transmitted multiframe related to the internal transmitter timing. in f12 + f72 format this interrupt will occur every 24 frames to inform the user that new bit robbing data has to written to xs1-12 registers. this interrupt will only be generated if the serial signaling access on the system highway is not enabled. rdo receive data overflow this interrupt status indicates that the cpu does not respond quickly enough to an rpf or rme interrupt and that data in rfifo has been lost. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsis.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor. alls all sent this bit is set if the last bit of the current frame is completely sent out and xfifo is empty. xdu transmit data underrun transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued. 70 isr1 case rdo alls xdu xmb xlsc xpr (x69)
semiconductor group 359 09.98 peb 22554 operational description t1 / j1 note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. xmb transmit multiframe begin this bit is set with the beginning of a transmitted multiframe related to the internal transmit line interface timing. xlsc transmit line status change xlsc is set to one with the rising edge of the bit frs1.xlo or with any change of bit frs1.xls. the actual status of the transmit line monitor can be read from the frs1.xls and frs1.xlo. xpr transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. interrupt status register 2 (read) all bits are reset when isr2 is read. if bit gcr.vis is set to 1, interrupt statuses in isr2 may be flagged although they are masked via register imr2. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. far frame alignment recovery the framer has reached synchronization. set with the falling edge of bit fsr0.lfa. it is set also after alarm simulation is finished and the receiver is still synchron. lfa loss of frame alignment the framer has lost synchronization and bit frs0.lfa is set. it will be set during alarm simulation. 70 isr2 far lfa mfar lmfa ais los rar ra (x6a)
semiconductor group 360 09.98 peb 22554 operational description t1 / j1 mfar multiframe alignment recovery set when the framer has reached multiframe alignment in f12 or f72 format. with the negative transition of bit frs0.lmfa this bit will be set. it will be set during alarm simulation. lmfa loss of multiframe alignment set when the framer has lost the multiframe alignment in f12 or f72 format. with the positive transition of bit frs0.lmfa this bit will be set. it will be set during alarm simulation. ais alarm indication signal (blue alarm) this bit is set when an alarm indication signal is detected and bit frs0.ais is set. if gcr.sci is set high this interrupt status bit will be activated with every change of state of frs0.ais. it will be set during alarm simulation. los loss of signal (red alarm) this bit is set when a loss of signal alarm is detected in the received data stream and frs0.los is set. if gcr.sci is set high this interrupt status bit will be activated with every change of state of frs0.los. it will be set during alarm simulation. rar remote alarm recovery set if a remote alarm (yellow alarm) is cleared and bit frs0.rra is reset. it is set also after alarm simulation is finished and no remote alarm is detected. ra remote alarm a remote alarm (yellow alarm) is detected. set with the rising edge of bit frs0.rra. it will be set during alarm simulation. interrupt status register 3 (read) all bits are reset when isr3 is read. if bit gcr.vis is set to 1, interrupt statuses in isr3 may be flagged although they are masked via register imr3. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. 7 0 isr3 es sec llbsc rsn rsp (x6b)
semiconductor group 361 09.98 peb 22554 operational description t1 / j1 es errored second this bit is set if at least one enabled interrupt source via esm is set during the time interval of one second. interrupt sources of esm register: lfa = loss of frame alignment detected fer = framing error received cer= crc error received ais = alarm indication signal (blue alarm) los = loss of signal (red alarm) cve = code violation detected slip= transmit slip or receive slip positive/negative detected sec second timer the internal one second timer has expired. the timer is derived from clock rclk. llbsc line loop back status change / prbs status change depending on bit lcr1.eprm the source of this interrupt status changed: lcr1.eprm=0: this bit is set to one, if the llb actuate signal or the llb deactuate signal respective is detected over a period of 33,16 msec with a bit error rate less than 1/100. the llbsc bit is also set to one, if the current detection status is left, i.e., if the bit error rate exceeds 1/100. the actual detection status can be read from the frs1.llbad and frs1.llbdd, respective. prbs status change lcr1.eprm=1: with any change of state of the prbs synchronizer this bit will be set. the current status of the prbs synchronizer is indicated in frs1.llbad. rsn receive slip negative the frequency of the receive route clock is greater than the frequency of the receive system interface working clock based on 1.544 mhz. a frame will be skipped. it will be set during alarm simulation. rsp receive slip positive the frequency of the receive route clock is less than the frequency of the receive system interface working clock based on 1.544 mhz. a frame will be repeated. it will be set during alarm simulation.
semiconductor group 362 09.98 peb 22554 operational description t1 / j1 interrupt status register 4(read) all bits are reset when isr4 is read. if bit gcr.vis is set to 1, interrupt statuses in isr4 may be flagged although they are masked via register imr4. however, these masked interrupt statuses neither generate a signal on int, nor are visible in register gis. xsp transmit slip positive the frequency of the transmit clock is less than the frequency of the transmit system interface working clock based on 1.544 mhz. a frame will be repeated. after a slip has performed writing of register xc1 is not necessary. xsn transmit slip negative the frequency of the transmit clock is greater than the frequency of the transmit system interface working clock based on 1.544 mhz. a frame will be skipped. after a slip has performed writing of register xc1 is not necessary. 7 0 isr4 xsp xsn (x6c)
semiconductor group 363 09.98 peb 22554 operational description t1 / j1 global interrupt status register (read) value after reset: 00 h this status register points to pending interrupts sourced by isr4 ... isr0. channel interrupt status register (read) value after reset: 00 h this status register points to pending interrupts sourced by the gis registers of each channel. gis4 ... register gis of falc4 gis3 ... register gis of falc3 gis2 ... register gis of falc2 gis1 ... register gis of falc1 70 gis isr4 isr3 isr2 isr1 isr0 (x6e) 70 cis gis4gis3gis2gis1 (6f)
semiconductor group 364 09.98 peb 22554 operational description t1 / j1 receive signaling register (read) value after reset: not defined receive signaling register 1-12 each register contains the received bit robbing information for 8 ds0 channels. the received robbed bit signaling information of a complete esf multiframe will be compared with the previously received one. in f12/72 frame format the received signaling information of every 24 frames will be compared with the previously received 24 frames. if the contents changed a receive signaling changed interrupt isr0.rsc is generated and informs the user that a new multiframe has to be read within the next 3 ms. received data will be stored in rs1-12 registers. the rs1.7 is received in channel 1 frame 1 and rs12.0 in channel 24 frame 24 (esf). if requests for reading the rs1-12 registers will be ignored the received data may be lost. additionally a receive signaling data change pointer indicates an update of register rs1-12 . refer also to register rsp1/2. access to rs1-12 registers is only valid if the serial receive signaling access on the system highway is disabled. 7 0 rs1 a1 b1 c1/a2 d1/b2 a2/a3 b2/b3 c2/a4 d2/b4 (x70) rs2 a3/a5 b3/b5 c3/a6 d3/b6 a4/a7 b4/b7 c4/a8 d4/b8 (x71) rs3 a5/a9 b5/b9 c5/a10 d5/b10 a6/a11 b6/b11 c6/a12 d6/b12 (x72) rs4 a7/a13 b7/b13 c7/a14 d7/b14 a8/a15 b8/b15 c8/a16 d8/b16 (x73) rs5 a9/a17 b9/b17 c9/a18 d9/b18 a10/a19 b10/b19 c10/a20 d10/b20 (x74) rs6 a11/a21 b11/b21 c11/a22 d11/b22 a12/a23 b12/b23 c12/a24 d12/b24 (x75) rs7 a13/a1 b13/b1 c13/a2 d13/b2 a14/a3 b14/b3 c14/a4 d14/b4 (x76) rs8 a15/a5 b15/b5 c15/a6 d15/b6 a16/a7 b16/b7 c16/a8 d16/b8 (x77) rs9 a17/a9 b17/b9 c17/a10 d17/b10 a18/a11 b18/b11 c18/a12 d18/b12 (x78) rs10 a19/a13 b19/b13 c19/a14 d19/b14 a20/a15 b20/b15 c20/a16 d20/b16 (x79) rs11 a21/a17 b21/b17 c21/a18 d21/b18 a22/a19 b22/b19 c22/a20 d22/b20 (x7a) rs12 a23/a21 b23/b21 c23/a22 d23/b22 a24/a23 b24/b23 c24/a24 d24/b24 (x7b)
peb 22554 preliminary electrical characteristics semiconductor group 365 09.98 9 preliminary electrical characteristics 9.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. v dd , v ddr and v ddx have to be connected to the same voltage level; v ss , v ssr and v ssx have to be connected to ground level. 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. parameter symbol limit values unit ambient temperature under bias t a C 40 to 85 c storage temperature t stg C 65 to 150 c ic supply voltage digital v dd C 0.3 to 5.5 v ic supply voltage receive v ddr C 0.3 to 5.5 v ic supply voltage transmit v ddx C 0.3 to 5.5 v voltage on any pin with respect to ground v s C 0.3 to 5 .5 v esd robustness 1) hbm: 1.5 k w , 100 pf v esd,hbm 1000 v parameter symbol limit values unit test condition min. max. ambient temperature t a - 40 85 c supply voltage digital v dd 3.135 3.465 v supply voltage receive v ddr 3.135 3.465 v supply voltage transmit v ddx 3.135 3.465 v ground digital v ss 00v ground receive v ssr 00v ground transmit v ssx 00v
peb 22554 preliminary electrical characteristics semiconductor group 366 09.98
peb 22554 semiconductor group 367 09.98 9.3 dc characteristics parameter symbol limit values unit notes min. max. input low voltage v il C 0.4 0.8 v 1) input high voltage v ih 2.0 v dd + 0.4 v 1) output low voltage v ol 0.45 v i ol =+ 2ma 1) output high voltage v oh 2.4 v i oh =- 2 ma 1) avg. power supply current (analog line interface) i dde1 i ddt1 300 350 ma ma e1 application 2) t1 application 3) avg. power supply current (digital line interface) i dd 90 ma sic1.ssc1/0 = 10 power down current i pd 10 ma register gcr.pd=0, all 4 single falcs input leakage current i il11 1 m a v in = v dd 4) input leakage current i il12 1 m a v in = v ss 4) input leakage current i il21 1 m a v in = v dd 5) input leakage current i il12 250 m a v in = v ss 5) output leakage current i oz 1 m a v out = tristate 1) v ss < v meas < v dd measures against v dd and v ss transmitter output impedance r x 3 w applies to xl1and xl2 6) transmitter output current i x 100 ma xl1, xl2 differential peak voltage of a mark (between xl1 and xl2) v x 2.15 v receiver differential peak voltage of a mark (between rl1 and rl2) v r v ddr +0.3 v rl1, rl2 receiver input impedance z r 50 (typical value) k w 6)
peb 22554 semiconductor group 368 09.98 1) applies to all pins except analog pins rlx, tlx 2) the power consumption of the device is calculated by the internal chip consumption minus the consumption of the external transmit line components. wiring conditions and external circuit configuration according to figure 11 ; values of registers: sic1.ssc1/0=00; xpm2-0 = bd h , 03 h , 00 h 3) the power consumption of the device is calculated by the internal chip consumption minus the consumption of the external transmit line components. wiring conditions and external circuit configuration according to figure 44 ; values of registers: sic1.ssc1/0=00; xpm2-0 = 9f h , 27 h , 02 h 4) applies to all pins except rclk, sclkr, sync, rpa, xpa, tdi, tms, tck, rl1, rl2, xl1, xl2 5) applies to pins rclk, sclkr, sync, rpa, xpa, tdi, tms, tck only 6) parameter not tested in production 7) differential input voltage between pins rl1 and rl2; depends on programming of register lim1.ril2-0 receiver sensitivity s rsh 0 10 db rl1, rl2 lim0.eqon=0 (short haul) receiver sensitivity s rlh 0 36 db rl1, rl2 lim0.eqon=1 (long haul) receiver input threshold v rth 55 (typical value) % 6) loss of signal threshold v los 0.90 0.70 0.60 0.40 0.30 0.20 0.10 0.05 (typical values) v ril2-0 = 000 ril2-0 = 001 ril2-0 = 010 ril2-0 = 011 ril2-0 = 100 ril2-0 = 101 ril2-0 = 110 ril2-0 = 111 6) 7) parameter symbol limit values unit notes min. max.
peb 22554 semiconductor group 369 09.98 9.4 ac characteristics 9.4.1 input/output waveforms for testing all inputs except rlx.y are driven to v ih = 2.4 v for a logical 1 and to v il = 0.4 v for a logical 0 timing measurements except for xlx.y are made at v h = 2.0 v for a logical 1 and at v l = 0.8 v for a logical 0 the ac testing input/output waveforms are shown below. figure 74 input/output waveform for ac testing 9.4.2 master clock timing figure 75 mclk timing table 32 mclk timing parameter values no. parameter limit values unit condition min. typ. max. 1 clock period of mclk 488 ns e1 648 ns t1 2 high phase of mclk 40 % 3 low phase of mclk 40 % clock accuracy 50 ppm v l its06467 h vv h l v test points under device test max = c load f p 100 2 1 3 mclk mclk 2.0 v 0.8 v
semiconductor group 370 09.98 peb 22554 9.4.3 jtag boundary scan interface figure 76 jtag boundary scan timing table 33 jtag boundary scan timing parameter values identification register : 32 bit; version: 1 h; part number: 4d h , manufacturer: 083 h no. parameter limit values unit min. max. 80 tck period 250 ns 81 tck high time 80 ns 82 tck low time 80 ns 83 tms setup time 40 ns 84 tms hold time 40 ns 85 tdi setup time 40 ns 86 tdi hold time 40 ns 87 tdo valid delay 100 ns 88 t rs active low 200 ns itt10943 81 82 80 tck tms tdo tdi 84 83 85 86 87 trs 88 ~ ~
peb 22554 semiconductor group 371 09.98 9.4.4 reset figure 77 reset timing table 34 reset timing parameter values 9.4.5 microprocessor interface 9.4.5.1 siemens/intel bus interface mode figure 78 siemens/intel non-multiplexed address timing note: ax = address pins a0 - a9 1) while mclk is running no. parameter limit values unit min. max. 1res pulse width low 10000 1) ns 1 res reset wr rd cs bhe ax 1 3 3a 2 itt10975
semiconductor group 372 09.98 peb 22554 figure 79 siemens/intel multiplexed address timing figure 80 siemens/intel read cycle timing wr rd 3 cs ale bhe ax 4 6 1 7 5 3a itt10977 7a cs itt06470 rd 8 9 12 wr float float 11 11a 10 d0 ... (d15...d8) d7
peb 22554 semiconductor group 373 09.98 figure 81 siemens/intel write cycle timing table 35 siemens/intel bus interface timing parameter values no. parameter limit values unit min. max. 1 address, bhe setup time 15 ns 2 address, bhe hold time 0 ns 3cs setup time 0 ns 3a cs hold time 0 ns 4 address, bhe stable before ale inactive 20 ns 5 address, bhe hold after ale inactive 10 ns 6 ale pulse width 30 ns 7 address latch setup time before cmd active 0 ns 7a ale to command inactive delay 30 ns 8rd pulse width 80 ns 9rd control interval 70 ns 10 data valid after rd active 75 ns 11 data hold after rd inactive 10 ns 11a rd inactive to data bus tristate 1) 30 ns 12 wr to rd or rd to wr control interval 70 ns d8) d7 d0 ... (d15... 16 itt06471 wr rd cs 15 13 14 12
semiconductor group 374 09.98 peb 22554 9.4.5.2 motorola bus interface mode figure 82 motorola read cycle timing 1) typical value, not tested in production 13 wr pulse width 80 ns 14 wr control interval 70 ns 15 data stable before wr inactive 30 ns 16 data hold after wr inactive 10 ns no. parameter limit values unit min. max. ds d7 d0 d8) ... (d15... float 24 25 25a float itt10976 rw cs 20 19 ble ax 17 19a 22 21 18 23
peb 22554 semiconductor group 375 09.98 figure 83 motorola write cycle timing table 36 motorola bus interface timing parameter values no. parameter limit values unit min. max. 17 address, ble , setup time before ds active 15 ns 18 address, ble , hold after ds inactive 0 ns 19 cs active before ds active 0 ns 19a cs hold after ds inactive 0 ns 20 rw stable before ds active 10 ns 21 rw hold after ds inactive 0 ns 22 ds pulse width (read access) 80 ns 22a ds pulse width (write access) 70 ns 23 ds control interval 70 ns 24 data valid after ds active (read access) 75 ns 25 data hold after ds inactive (read access) 10 ns ds ... d0 (d15 d7... d8) 26 rw cs ax ble 20 19 17 22a 27 itt10974 21 19a 18 23
semiconductor group 376 09.98 peb 22554 9.4.6 line interface figure 84 timing of dual rail optical interface 1) typical value, not tested in production 25a ds inactive to databus tristate (read access) 1) 30 ns 26 data stable before ds active (write access) 30 ns 27 data hold after ds inactive (write access) 10 ns no. parameter limit values unit min. max. cmi coding xdon/ xdop/ xoid/ xoid 1) 1) 38 38a xclk roid rclki 37 32 35 33 36 34 30 31 itt10978 xfm
peb 22554 semiconductor group 377 09.98 table 37 dual rail optical interface parameter values no. parameter limit values unit e1 t1 min. typ. max. min. typ. max. 30 rclki clock period 488 648 ns 31 rclki clock period low 180 240 ns 32 rclki clock period high 180 240 ns 33 roid setup 50 50 ns 34 roid hold 50 50 ns 35 xclk clock period 488 648 ns 36 xclk clock period low xclk clock period low 4) 190 150 230 200 ns 37 xclk clock period high xclk clock period high 4) 190 150 230 200 ns 38 xoid delay 1) xdop/xdon delay 2) 60 60 ns 38a xoid delay 3) 60 60 ns rclk (output) 488 122 648 162 ns ns rclk clock period low 40 60 40 60 % rclk clock period high 40 60 40 60 % 1) nrz coding 2) hdb3/ami/b8zs coding 3) cmi coding 4) depends on input rclki in optical interface and remote loop without transmit jitter attenuator enabled (lim1.jatt/rl=01).
semiconductor group 378 09.98 peb 22554 9.4.7 system interface figure 85 rclk, rfsp output timing table 38 rclk, rfsp timing parameter values no. parameter limit values unit min. typ. max. 1 rclk period e1 (2.048 mhz) 488 ns rclk period e1 (2.048 mhz x 4) 122 ns rclk period t1 (1.544 mhz) 648 ns rclk period t1 (1.544 mhz x 4) 162 ns 2 rclk pulse high 40 60 % 3 rclk pulse low 40 60 % 4rfsp delay 80 ns rclk (output) rfsp 4 1) active edge can be programmed to be positive or negative (only negative edge timing shown here) valid only, if rclk is derived from dpll (not, if rclk is jitter attenuated) data valid rfsp 2 1 3
peb 22554 semiconductor group 379 09.98 figure 86 sclkr/sclkx input timing table 39 sclkr/sclkx timing parameter values no. parameter limit values unit min. typ. max. 1 sxlkr/sclkx period at 16.384 mhz 61 ns 1 sxlkr/sclkx period at 8.192 mhz 122 ns 1 sxlkr/sclkx period at 4.096 mhz 244 ns 1 sxlkr/sclkx period at 2.048 mhz 488 ns 1 sxlkr/sclkx period at 12.352 mhz 81 ns 1 sxlkr/sclkx period at 6.176 mhz 162 ns 1 sxlkr/sclkx period at 3.088 mhz 324 ns 1 sxlkr/sclkx period at 1.544 mhz 648 ns 2 sclkr/sclkx pulse high 40 % 3 sclkr/sclkx pulse low 40 % 2 1 3 sclkr sclkx (input) sclkrx_input
semiconductor group 380 09.98 peb 22554 figure 87 system interface marker timing (receive) table 40 system interface marker timing parameter values no. parameter limit values unit min. typ. max. 1 rdo, rsig delay 100 ns 2 rsigm, rmfb, dlr, rfm, freeze marker delay 100 ns 1 1) active edge can be programmed to be positive or negative 2 data valid rdo, rsig, rsigm, dlr, rfm, rfmb, freeze sclkr (input) receive marker 1 2 data valid positive edge timing 1) negative edge timing 1)
peb 22554 semiconductor group 381 09.98 figure 88 sypr , sypx timing table 41 sypr /sypx timing parameter values 1) typical value, not testd in production no. parameter limit values unit min. typ. max. 1 sclkr period (t 1 ) 61 648 ns 2 sypr /sypx inactive setup time 1) 4 x t 1 ns 3 sypr /sypx setup time 5 ns 4 sypr /sypx hold time 50 ns active edge 2 4 3 inactive active low sclkr (input) sypr, sypx sypr 1
semiconductor group 382 09.98 peb 22554 figure 89 system interface marker timing (transmit) table 42 system interface marker timing parameter values no. parameter limit values unit min. typ. max. 1 xmfb, dlx, xsigm delay 100 ns active edge 1) sclkx, sclkr xmfb, dlx, xsigm 1 1) active edge can be programmed to be positive or negative (only negative edge timing shown here) xmfb
peb 22554 semiconductor group 383 09.98 figure 90 xdi, xsig timing table 43 xdi, xsig timing parameter values no. parameter limit values unit min. typ. max. 1 xsig, xdi setup time 5 ns 2 xsig, xdi hold time 55 ns active edge 1) sclkx, sclkr xdi, xsig 1) active edge can be programmed to be positive or negative (only negative edge timing shown here) 1 2 transmit marker
semiconductor group 384 09.98 peb 22554 figure 91 xmfs timing table 44 xmfs timing parameter values 1) depending on application 2) typical value, not tested in production no. parameter limit values unit min. typ. max. 1 sclkr/sclkx period (t 1 ) 1) ns 2 xmfs inactive setup time 2) 4 x t 1 ns 3 xmfs setup time 5 ns 4 xmfs hold time 50 ns sclkx, sclkr xmfs 4 3 2 xmfs 1
peb 22554 semiconductor group 385 09.98 figure 92 tclk input timing table 45 tclk timing parameter values no. parameter limit values unit min. typ. max. 1 tclk period e1 (2.048 mhz) 488 ns tclk period e1 (2.048 mhz x 4) 122 ns tclk period t1 (1.544 mhz) 648 ns tclk period t1 (1.544 mhz x 4) 162 ns 2 tclk high 40 % 3tclk low 40 % 2 1 3 tclk tclk
semiconductor group 386 09.98 peb 22554 figure 93 xclk timing table 46 xclk timing parameter values 1) depends on input rclki in optical interface and remote loop without transmit jitter attenuator enabled (lim1.jatt/rl=01) no. parameter limit values unit e1 t1 min. typ. max. min. typ. max. 1 xclk delay 100 100 ns 2 xclk clock period low 190 230 ns xclk clock period low 1) 150 200 ns 3 xclk clock period high 190 230 ns xclk clock period high 1) 150 200 ns sclkx, sclkr xclk xclk 1 2 3
peb 22554 semiconductor group 387 09.98 figure 94 sec timing table 47 sec timing parameter values no. parameter limit values unit min. typ. max. 1 sec input period e1 1 s 2 sec input high e1 976 ns sec input high t1 1296 ns 3 sec input low e1 976 ns sec input low t1 1296 ns 4 sec output period 1 s 5 sec high output e1 976 ns sec high output t1 1296 ns 2 1 3 sec (input) 5 4 sec (output) 1) 1) clock running continuously second clock
semiconductor group 388 09.98 peb 22554 figure 95 fsc timing table 48 fsc timing parameter values no. parameter limit values unit min. typ. max. 1 fsc period 125 s 2 fsc low time e1 488 ns 2 fsc low time t1 648 ns 2 1 fsc fsc high
peb 22554 semiconductor group 389 09.98 9.4.8 pulse templates - transmitter 9.4.8.1 pulse template e1 figure 96 e1 pulse shape at transmitter output for cept applications itd00573 10 % 10 % % 10 10 % % 10 10 % 20 % 269 ns (244 + 25) (244 - 50) ns 194 219 ns (244 - 25) ns 244 (244 + 244) ns 488 % 0 50 % % v =100 nominal pulse % 20 20 %
semiconductor group 390 09.98 peb 22554 9.4.8.2 pulse template t1 figure 97 t1 pulse shape at the cross connect point table 49 t1 pulse template corner points at the cross connect point (t1.102) 100 % value must be in the range between 2.4 v and 3.6 v. maximum curve time [ns] v [%] minimum curve time [ns] v [%] ( 0, 0.05) ( 250, 0.05) ( 325, 0.80) ( 325, 1.15) ( 425, 1.15) ( 500, 1.05) ( 675, 1.05) ( 725, -0.07) ( 1100, 0.05) ( 1250, 0.05) ( 0, -0.05) ( 350, -0.05) ( 350, 0.5) ( 400, 0.95) ( 500, 0.95) ( 600, 0.90) ( 650, 0.50) ( 650, -0.45) ( 800, -0.45) ( 925, -0.2) ( 1100, -0.05) ( 1250, -0.05) itd00574 % 100 = v 50 % 0 -50 % 0 250 500 750 1000 ns t normalized amplitude
peb 22554 semiconductor group 391 09.98 9.5 capacitances parameter symbol limit values unit pins typ. max. input capacitance 1) c in 510pf output capacitance 1) c out 8 15 pf all except xlx.y output capacitance 1) c out 820pfxlx.y 1) not tested in production.
peb 22554 package outlines semiconductor group 392 09.98 10 package outlines p-mqfp-144-8 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device
peb 22554 glossary semiconductor group 393 09.98 11 glossary adc analog to digital converter ais alarm indication signal (blue alarm) agc automatic gain control alos analog loss of signal ami alternate mark inversion ansi american national standards institute atm asynchronous transfer mode auxp auxiliary pattern b8zs line coding to avoid too long strings of consecutive 0 ber bit error rate bfa basic frame alignment bom bit orientated message bellcore bell communications research bpv bipolar violation cas channel associated signaling cas-br channel associated signaling - bit robbing cas-cc channel associated signaling - common channel ccs common channel signaling crc4 cyclic redundancy check csu channel service unit cvc code violation counter dco digitally controlled oscillator dl digital loop dpll digitally controlled phase locked loop
peb 22554 glossary semiconductor group 394 09.98 ds1 digital signal level 1 esd electrostatic discharge esf extended superframe (f24) format eq equalizer etsi eurpean telecommunication standards institute falc ? framing and line interface component fas frame alignment sequence fcc us federal communication commission fcs frame check sequence fisu fill in signaling unit fps framing pattern sequence hbm human body model for esd classification hdb3 high density bipolar of order 3 hdlc high level data link control ibl in band loop (=llb) isdn intergrated sevices digital network itu international telecommunications group jatt jitter attenuator jtag joined test action group lbo line build out lcv line code violation liu line interface unit lfa loss of frame alignment ll local loop llb line loop back (= ibl) los loss of signal (red alarm)
peb 22554 glossary semiconductor group 395 09.98 lsb least significant bit lssu link status signaling unit mf multiframe msb most significant bit msu message signaling unit nrz non return to zero signal pdv pulse density violation plb payload loop back pll phase locked loop pmqfp plastic metric quad flat pack (device package) ppr periodical performance report prbs pseudo ramdom binary sequence ptqfp plastic thin metric quad flat pack (device package) rai remote alarm indication (yellow alarm) rl remote loop sf superframe sidactor overvoltage protection device for transmission lines tap test access port ui unit interval
peb 22554 appendix semiconductor group 396 09.98 12 appendix 12.1 protection circuitry the design in figure 98 is a suggestion how to build up a generic e1/t1 platform. with the selection of the appropriate components the same circuitry is also able to handle the return loss and impedance to ground requirements of etsi. for more details of this circuits, please refer to the appropriate application notes listed on the following page. figure 98 protection circuitry its10821 falc r w 10 10 w rl2 rl1 v cc gnd 2 r w2 : w1 gnd xl2 v cc xl1 gnd w1 w2 : sidactor 3 r 1 r 1 r diodes gnd sidactor fuse r 3 fuse 3 r r 3 fuse fuse
peb 22554 appendix semiconductor group 397 09.98 12.2 application notes the following application notes and technical documentation provide additional information: ? transformer recommendation ? transmit pulse shape programming ? frequently asked questions ? designing a generic e1/t1 platform for short haul and long haul applications ? different hints to pass ets300 011 ? key features and applications 12.3 software support the following software package is provided together with the falc evaluation system easy22554: ? application wizard ? e1 driver functions supporting different etsi requirements including hdlc signaling ? lapd signaling software ? fdl signaling software ? boundary scan file ? ibis model

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